Searched refs:BFM (Results 1 - 9 of 9) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.h | 420 BFM, // Insert a range of bits into a 32-bit word.
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| H A D | SIISelLowering.cpp | 3676 // Since BFM can't shift by 64, handle that case with CMP + CMOV. in EmitInstrWithCustomInserter()
4868 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT()
4872 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
4874 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
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| H A D | AMDGPUISelLowering.cpp | 4285 NODE_NAME_CASE(BFM) in getTargetNodeName()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1917 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64); in tryBitfieldExtractOp() local
1920 MVT::i32, SDValue(BFM, 0), SubReg)); in tryBitfieldExtractOp()
2307 // BFI/BFXIL is an alias of BFM, so translate to BFM operands. in tryBitfieldInsertOpFromOrAndImm()
2369 // f = BFM Opd0, Opd1, LSB, MSB ; where LSB = imm, and MSB = imm2 in tryBitfieldInsertOpFromOr()
2490 // BFXIL is an alias of BFM, so translate to BFM operands. in tryBitfieldInsertOpFromOr()
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| H A D | AArch64InstructionSelector.cpp | 2861 MachineInstr &BFM = in selectMergeValues() local
2870 constrainSelectedInstRegOperands(BFM, TII, TRI, RBI); in selectMergeValues()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | constants-arm64.h | 678 BFM = BFM_w,
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| H A D | assembler-arm64.cc | 986 Emit(SF(rd) | BFM | N | ImmR(immr, rd.SizeInBits()) | in bfm()
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| /third_party/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 830 BFM = BFM_w, enumerator
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| H A D | assembler-aarch64.cc | 686 Emit(SF(rd) | BFM | N | ImmR(immr, rd.GetSizeInBits()) | in bfm()
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