Searched refs:AreSameFormat (Results 1 - 9 of 9) sorted by relevance
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 276 bool AreSameFormat(const VRegister& reg1, const VRegister& reg2, in AreSameFormat() function
1435 DCHECK(AreSameFormat(vn, vm)); in NEON3DifferentL()
1452 DCHECK(AreSameFormat(vd, vn)); in NEON3DifferentW()
1461 DCHECK(AreSameFormat(vm, vn)); in NEON3DifferentHN()
1536 DCHECK(AreSameFormat(vd, vn, vm)); in NEONPerm()
1573 DCHECK(AreSameFormat(vd, vn)); in NEONShiftImmediate()
1939 DCHECK(AreSameFormat(vd, vn)); in cls()
1945 DCHECK(AreSameFormat(vd, vn)); in clz()
1951 DCHECK(AreSameFormat(vd, vn)); in cnt()
1957 DCHECK(AreSameFormat(v in rev16()
[all...] |
| H A D | register-arm64.h | 529 // AreSameFormat returns true if all of the specified VRegisters have the same
532 bool AreSameFormat(const VRegister& reg1, const VRegister& reg2,
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 322 VIXL_ASSERT(AreSameFormat(vd, vm)); in NEONTable()
341 VIXL_ASSERT(AreSameFormat(vn, vn2)); in tbl()
354 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3)); in tbl()
368 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3, vn4)); in tbl()
388 VIXL_ASSERT(AreSameFormat(vn, vn2)); in tbx()
401 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3)); in tbx()
415 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3, vn4)); in tbx()
1657 VIXL_ASSERT(AreSameFormat(rs, rt)); \
1708 VIXL_ASSERT(AreSameFormat(rs, rs1, rt, rt1)); \
2599 VIXL_ASSERT(AreSameFormat(v in ld1()
[all...] |
| H A D | assembler-sve-aarch64.cc | 135 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in and_()
144 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in bic()
153 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in eor()
162 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in orr()
2345 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in add()
2361 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in and_()
2377 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in bic()
2393 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in eor()
2409 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in mul()
2425 VIXL_ASSERT(AreSameFormat(z in orr()
[all...] |
| H A D | operands-aarch64.h | 633 AreSameFormat(base_, regoffset_) && in IsVectorPlusVector()
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| H A D | registers-aarch64.h | 1108 // AreSameFormat returns true if all of the specified registers have the same
1112 bool AreSameFormat(const CPURegister& reg1,
1128 // TODO: Remove this, and replace its uses with AreSameFormat.
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| H A D | macro-assembler-aarch64.h | 4207 VIXL_ASSERT(AreSameFormat(zd, zn)); in Decp()
4932 VIXL_ASSERT(AreSameFormat(zd, zn)); in Incp()
5930 VIXL_ASSERT(AreSameFormat(zd, zn)); in Sqdecp()
6019 VIXL_ASSERT(AreSameFormat(zd, zn)); in Sqincp()
6354 VIXL_ASSERT(AreSameFormat(zd, zn)); in Uqdecp()
6418 VIXL_ASSERT(AreSameFormat(zd, zn)); in Uqincp()
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| H A D | macro-assembler-sve-aarch64.cc | 1058 VIXL_ASSERT(AreSameFormat(pd, pn)); in Pnext()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.h | 456 VIXL_ASSERT(AreSameFormat(expected, result));
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