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Searched refs:And (Results 1 - 25 of 334) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMaskingPreRA.cpp208 auto *And = TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, in optimizeVcndVcmpPair()
210 if (!And || And->getOpcode() != AndOpc || in optimizeVcndVcmpPair()
211 !And->getOperand(1).isReg() || !And->getOperand(2).isReg()) in optimizeVcndVcmpPair()
214 MachineOperand *AndCC = &And->getOperand(1); in optimizeVcndVcmpPair()
218 AndCC = &And->getOperand(2); in optimizeVcndVcmpPair()
221 } else if (And->getOperand(2).getReg() != ExecReg) { in optimizeVcndVcmpPair()
225 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, MRI, LIS); in optimizeVcndVcmpPair()
228 Cmp->getParent() != And in optimizeVcndVcmpPair()
255 << *And); optimizeVcndVcmpPair() local
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H A DSILowerControlFlow.cpp225 MachineInstr *And = in emitIf() local
230 setImpSCCDefDead(*And, true); in emitIf()
261 LIS->ReplaceMachineInstrInMaps(MI, *And); in emitIf()
311 MachineInstr *And = in emitElse() local
317 LIS->InsertMachineInstrInMaps(*And); in emitElse()
373 MachineInstr *And = nullptr, *Or = nullptr; in emitIfBreak() local
376 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg) in emitIfBreak()
390 if (And) in emitIfBreak()
391 LIS->InsertMachineInstrInMaps(*And); in emitIfBreak()
H A DAMDGPUAtomicOptimizer.cpp124 case AtomicRMWInst::And: in visitAtomicRMWInst()
181 Op = AtomicRMWInst::And; in visitIntrinsicInst()
257 case AtomicRMWInst::And: in buildNonAtomicBinOp()
258 return B.CreateBinOp(Instruction::And, LHS, RHS); in buildNonAtomicBinOp()
397 case AtomicRMWInst::And: in getIdentityValueForAtomicOp()
531 case AtomicRMWInst::And: in optimizeAtomic()
628 case AtomicRMWInst::And: in optimizeAtomic()
657 // And delete the original. in optimizeAtomic()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
H A DGuardUtils.cpp87 auto *And = dyn_cast<Instruction>(Cond); in parseWidenableBranch()
88 if (!And) in parseWidenableBranch()
94 WC = &And->getOperandUse(0); in parseWidenableBranch()
95 C = &And->getOperandUse(1); in parseWidenableBranch()
101 WC = &And->getOperandUse(1); in parseWidenableBranch()
102 C = &And->getOperandUse(0); in parseWidenableBranch()
/third_party/typescript/tests/baselines/reference/
H A DconditionalTypes1.js172 type And<A extends boolean, B extends boolean> = If<A, B, false>;
186 type A1 = And<false, false>; // false
187 type A2 = And<false, true>; // false
188 type A3 = And<true, false>; // false
189 type A4 = And<true, true>; // true
190 type A5 = And<boolean, false>; // false
191 type A6 = And<false, boolean>; // false
192 type A7 = And<boolean, true>; // boolean
193 type A8 = And<true, boolean>; // boolean
194 type A9 = And<boolea
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h72 template <typename... Preds> struct And { struct
80 struct And<Pred, Preds...> : And<Preds...> { struct
82 And(Pred &&p, Preds &&... preds) in And() function
83 : And<Preds...>(std::forward<Preds>(preds)...), P(std::forward<Pred>(p)) { in And()
87 return P.match(MRI, src) && And<Preds...>::match(MRI, src); in match()
109 template <typename... Preds> And<Preds...> m_all_of(Preds &&... preds) { in m_all_of()
110 return And<Preds...>(std::forward<Preds>(preds)...); in m_all_of()
/third_party/vixl/test/aarch32/
H A Dtest-assembler-aarch32.cc515 __ And(r3, r0, r1); in TEST()
516 __ And(r4, r0, Operand(r1, LSL, 4)); in TEST()
517 __ And(r5, r0, Operand(r1, LSR, 1)); in TEST()
518 __ And(r6, r0, Operand(r1, ASR, 20)); in TEST()
519 __ And(r7, r0, Operand(r1, ROR, 28)); in TEST()
520 __ And(r8, r0, 0xff); in TEST()
524 __ And(r9, r1, Operand(r1, RRX)); in TEST()
528 __ And(r10, r1, Operand(r1, RRX)); in TEST()
2948 __ And(r3, r3, 0xf0000000); in TEST()
3035 __ And(r in TEST()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
H A DInstCombineAtomicRMW.cpp44 case AtomicRMWInst::And: in isIdempotentRMW()
82 case AtomicRMWInst::And: in isSaturating()
H A DInstCombineCompares.cpp1633 Instruction *InstCombiner::foldICmpAndShift(ICmpInst &Cmp, BinaryOperator *And, in foldICmpAndShift() argument
1635 BinaryOperator *Shift = dyn_cast<BinaryOperator>(And->getOperand(0)); in foldICmpAndShift()
1663 // the And doesn't use any bits being shifted in. Normally these would in foldICmpAndShift()
1686 Cmp.setOperand(1, ConstantInt::get(And->getType(), NewCst)); in foldICmpAndShift()
1688 And->setOperand(1, ConstantInt::get(And->getType(), NewAndCst)); in foldICmpAndShift()
1689 And->setOperand(0, Shift->getOperand(0)); in foldICmpAndShift()
1703 IsShl ? Builder.CreateLShr(And->getOperand(1), Shift->getOperand(1)) in foldICmpAndShift()
1704 : Builder.CreateShl(And->getOperand(1), Shift->getOperand(1)); in foldICmpAndShift()
1717 BinaryOperator *And, in foldICmpAndConstConst()
1716 foldICmpAndConstConst(ICmpInst &Cmp, BinaryOperator *And, const APInt &C1) foldICmpAndConstConst() argument
1825 foldICmpAndConstant(ICmpInst &Cmp, BinaryOperator *And, const APInt &C) foldICmpAndConstant() argument
2104 Value *And = Builder.CreateAnd(X, Mask, Shl->getName() + ".mask"); foldICmpShlConstant() local
2116 Value *And = Builder.CreateAnd(X, Mask, Shl->getName() + ".mask"); foldICmpShlConstant() local
2126 Value *And = Builder.CreateAnd(X, (~C).lshr(ShiftAmt->getZExtValue())); foldICmpShlConstant() local
2134 Value *And = foldICmpShlConstant() local
2249 Value *And = Builder.CreateAnd(X, Mask, Shr->getName() + ".mask"); foldICmpShrConstant() local
2280 Value *And = Builder.CreateAnd(SRem->getOperand(0), MaskC); foldICmpSRemConstant() local
2984 Value *And = Builder.CreateAnd(BOp0, NotBOC); foldICmpBinOpEqualityWithConstant() local
4267 Value *And = Builder.CreateAnd(Xor, Builder.getInt(AndVal), foldICmpEquality() local
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H A DInstCombineCasts.cpp180 case Instruction::And: in EvaluateInDifferentType()
355 case Instruction::And: in canEvaluateTruncated()
593 case Instruction::And: in narrowBinOp()
732 Value *And = Builder.CreateAnd(Src, ConstantInt::get(SrcTy, 1)); in visitTrunc() local
733 return new ICmpInst(ICmpInst::ICMP_NE, And, Zero); in visitTrunc()
743 Value *And = Builder.CreateAnd(X, ConstantInt::get(SrcTy, MaskC)); in visitTrunc() local
744 return new ICmpInst(ICmpInst::ICMP_NE, And, Zero); in visitTrunc()
750 Value *And = Builder.CreateAnd(X, ConstantInt::get(SrcTy, MaskC)); in visitTrunc() local
751 return new ICmpInst(ICmpInst::ICMP_NE, And, Zero); in visitTrunc()
998 case Instruction::And in canEvaluateZExtd()
1158 Value *And = Builder.CreateAnd(A, AndConst, CSrc->getName() + ".mask"); visitZExt() local
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H A DInstCombineAndOrXor.cpp916 /// And X is checking that some bit in that same mask is zero.
931 assert(CxtI.getOpcode() == Instruction::And); in foldSignedTruncationCheck()
981 // And the other icmp needs to be decomposable into a bit test. in foldSignedTruncationCheck()
1416 assert((Opcode == Instruction::And || Opcode == Instruction::Or) && in reassociateFCmps()
1428 FCmpInst::Predicate NanPred = Opcode == Instruction::And ? FCmpInst::FCMP_ORD in reassociateFCmps()
1461 assert((Opcode == Instruction::And || Opcode == Instruction::Or) && in matchDeMorgansLaws()
1465 Opcode = (Opcode == Instruction::And) ? Instruction::Or : Instruction::And; in matchDeMorgansLaws()
1583 Value *Res = LogicOpc == Instruction::And ? foldAndOfICmps(ICmp0, ICmp1, I) in foldCastedBitwiseLogic()
1595 if (Value *R = foldLogicOfFCmps(FCmp0, FCmp1, LogicOpc == Instruction::And)) in foldCastedBitwiseLogic()
1681 narrowMaskedBinOp(BinaryOperator &And) narrowMaskedBinOp() argument
1766 Value *And = Builder.CreateAnd(X, Op1); visitAnd() local
1780 Value *And = Builder.CreateAnd(X, ConstantInt::get(I.getType(), visitAnd() local
1839 auto *And = Builder.CreateAnd(BinOp, TruncC2); visitAnd() local
3080 Value *And = Builder.CreateAnd(X, ConstantExpr::getNot(C2)); visitXor() local
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H A DInstCombineShifts.cpp243 // And compute the mask as usual: ~(-1 << (SumOfShAmts)) in dropRedundantMaskingOfLeftShiftInput()
281 // And compute the mask as usual: (-1 l>> (NumHighBitsToClear)) in dropRedundantMaskingOfLeftShiftInput()
316 return BinaryOperator::Create(Instruction::And, NewShift, NewMask); in dropRedundantMaskingOfLeftShiftInput()
515 case Instruction::And: in canEvaluateShifted()
590 Value *And = Builder.CreateAnd(InnerShift->getOperand(0), in foldShiftedShift() local
592 if (auto *AndI = dyn_cast<Instruction>(And)) { in foldShiftedShift()
596 return And; in foldShiftedShift()
632 case Instruction::And: in getShiftedValue()
677 case Instruction::And: in canShiftBinOpWithConstantRHS()
749 Value *And in FoldShiftByConstant() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/AggressiveInstCombine/
H A DTruncInstCombine.cpp53 case Instruction::And: in getRelevantOperands()
115 case Instruction::And: in buildTruncExpressionDag()
346 case Instruction::And: in ReduceExpressionDag()
H A DAggressiveInstCombine.cpp246 Value *And = Builder.CreateAnd(MOps.Root, Mask); in foldAnyOrAllBitsSet() local
247 Value *Cmp = MatchAllBitsSet ? Builder.CreateICmpEQ(And, Mask) in foldAnyOrAllBitsSet()
248 : Builder.CreateIsNotNull(And); in foldAnyOrAllBitsSet()
/third_party/rust/crates/syn/src/
H A Dop.rs17 And(Token![&&]),
108 input.parse().map(BinOp::And) in parse()
181 BinOp::And(t) => t.to_tokens(tokens), in to_tokens()
/third_party/vixl/examples/aarch64/
H A Dneon-matrix-multiply.cc68 __ And(x3, x0, x1); in GenerateNEONMatrixMultiply()
69 __ And(x3, x3, x2); in GenerateNEONMatrixMultiply()
H A Dgetting-started.cc42 __ And(x0, x0, x1); in GenerateDemoFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
H A DInstruction.h176 return Opcode == And || Opcode == Or || Opcode == Xor; in isBitwiseLogicOp()
483 /// In LLVM, the Add, Mul, And, Or, and Xor operators are associative.
487 return Opcode == And || Opcode == Or || Opcode == Xor || in isAssociative()
503 case And: case Or: case Xor: in isCommutative()
514 /// In LLVM, the And and Or operators are idempotent.
518 return Opcode == And || Opcode == Or; in isIdempotent()
/third_party/vixl/examples/aarch32/
H A Dgetting-started.cc39 __ And(r0, r0, r1); in GenerateDemo()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/
H A DLocked.cpp49 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Dst1, \ in TEST_F()
99 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
101 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Reg1, \ in TEST_F()
158 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Dst1, \ in TEST_F()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8664/
H A DLocked.cpp47 __ And(IceType_i32, Encoded_GPR_##Dst1(), Immediate(Mask##Size)); \ in TEST_F()
99 __ And(IceType_i32, Encoded_GPR_##Reg0(), Immediate(Mask##Size)); \ in TEST_F()
100 __ And(IceType_i32, Encoded_GPR_##Reg1(), Immediate(Mask##Size)); \ in TEST_F()
157 __ And(IceType_i32, Encoded_GPR_##Dst1(), Immediate(Mask##Size)); \ in TEST_F()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp53 case Instruction::And: in getIntImmCostInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp886 // And for the inverse: in scanSelect()
985 case Instruction::And: in isPromotableTo()
1040 Value *And = IRBuilder<>(In).CreateAnd(T->getOperand(0), Mask); in promoteTo() local
1041 T->replaceAllUsesWith(And); in promoteTo()
1237 case Instruction::And: in commutesWithShift()
1272 case Instruction::And: in keepsHighBitsZero()
1580 case Instruction::And: in hasZeroSignBit()
1597 case Instruction::And: in setupPreSimplifier()
1618 if (And0->getOpcode() != Instruction::And || in setupPreSimplifier()
1619 And1->getOpcode() != Instruction::And) in setupPreSimplifier()
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/third_party/vixl/benchmarks/aarch64/
H A Dbench-utils.cc220 __ And(PickR(size), PickR(size), Operand(PickR(size))); in GenerateOperandSequence()
274 __ And(PickR(size), PickR(size), GetRandomBits(size)); in GenerateImmediateSequence()
379 __ And(PickV().V16B(), PickV().V16B(), PickV().V16B()); in GenerateNEONSequence()
/third_party/rust/crates/nom/src/
H A Dinternal.rs287 fn and<G, O2>(self, g: G) -> And<Self, G> in source()
292 And { f: self, g } in source()
393 pub struct And<F, G> { structure names
399 for And<F, G>

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