| /third_party/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 627 COMPARE_T32(Adcs(r0, r0, Operand(r2, LSR, r3)), in TEST()
1528 COMPARE_BOTH(Adcs(r0, r1, -2), "sbcs r0, r1, #1\n"); in TEST()
2614 COMPARE_A32(Adcs(pc, r0, 1), "adcs pc, r0, #1\n"); in TEST()
2615 COMPARE_A32(Adcs(r0, pc, 1), "adcs r0, pc, #1\n"); in TEST()
2616 MUST_FAIL_TEST_T32(Adcs(pc, r0, 1), "Unpredictable instruction.\n"); in TEST()
2617 MUST_FAIL_TEST_T32(Adcs(r0, pc, 1), "Unpredictable instruction.\n"); in TEST()
2626 COMPARE_A32(Adcs(pc, r0, r1), "adcs pc, r0, r1\n"); in TEST()
2627 COMPARE_A32(Adcs(r0, pc, r1), "adcs r0, pc, r1\n"); in TEST()
2628 COMPARE_A32(Adcs(r0, r1, pc), "adcs r0, r1, pc\n"); in TEST()
2629 MUST_FAIL_TEST_T32(Adcs(p in TEST()
[all...] |
| H A D | test-assembler-aarch32.cc | 296 __ Adcs(r3, r2, r1); in TEST()
311 __ Adcs(r3, r2, Operand(r1, ASR, 31)); in TEST()
326 __ Adcs(r3, r2, Operand(r1, LSR, 31)); in TEST()
341 __ Adcs(r3, r2, Operand(r1, LSL, 4)); in TEST()
356 __ Adcs(r3, r2, Operand(r1, ROR, 8)); in TEST()
371 __ Adcs(r3, r2, Operand(r1, RRX)); in TEST()
386 __ Adcs(r3, r2, Operand(r1, RRX)); in TEST()
6081 // CHECK_SIZE_MATCH(Adcs(r7, r6, r7),
6082 // Adcs(r7, r7, r6));
6084 // CHECK_SIZE_MATCH(Adcs(e
[all...] |
| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 117 M(Adcs) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 117 M(Adcs) \
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| H A D | test-simulator-cond-rd-rn-operand-const-a32.cc | 117 M(Adcs) \
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| H A D | test-simulator-cond-rd-rn-operand-const-t32.cc | 117 M(Adcs) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 117 M(Adcs) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 117 M(Adcs) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 117 M(Adcs) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 117 M(Adcs) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 117 M(Adcs) \
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 198 void MacroAssembler::Adcs(const Register& rd, const Register& rn, in Adcs() function in v8::internal::MacroAssembler
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| H A D | macro-assembler-arm64.h | 1537 inline void Adcs(const Register& rd, const Register& rn,
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 5392 AdcsSbcsHelper(&MacroAssembler::Adcs,
5398 AdcsSbcsHelper(&MacroAssembler::Adcs,
5582 AdcsSbcsHelper(&MacroAssembler::Adcs,
5588 AdcsSbcsHelper(&MacroAssembler::Adcs,
5749 __ Adcs(x10, x0, Operand(x1, SXTX, 1));
5763 __ Adcs(x10, x0, Operand(x1, UXTB, 2));
5776 __ Adcs(x10, x0, Operand(1));
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| H A D | test-disasm-aarch64.cc | 2887 COMPARE_MACRO(Adcs(x0, xzr, Operand(w1, SXTW)), in TEST()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.cc | 1949 void MacroAssembler::Adcs(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-aarch64.h | 829 void Adcs(const Register& rd, const Register& rn, const Operand& operand);
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 1156 Adcs(cond, rd, rn, operand); in MacroAssembler()
1163 Adcs(cond, rd, rn, operand); in MacroAssembler()
1177 void Adcs(Condition cond, Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1191 void Adcs(Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1192 Adcs(al, rd, rn, operand); in MacroAssembler()
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