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Searched refs:ASSERT_EQUAL_64 (Results 1 - 8 of 8) sorted by relevance

/third_party/vixl/test/aarch64/
H A Dtest-assembler-aarch64.cc99 ASSERT_EQUAL_64(0x1000, x0); in TEST()
100 ASSERT_EQUAL_64(0x207de, x1); in TEST()
101 ASSERT_EQUAL_64(0x10000ff1, x2); in TEST()
102 ASSERT_EQUAL_64(0x19001, x3); in TEST()
103 ASSERT_EQUAL_64(0x10000ff1, x4); in TEST()
104 ASSERT_EQUAL_64(0xfffffffffffe1822, x5); in TEST()
105 ASSERT_EQUAL_64(0xf000100f, x6); in TEST()
106 ASSERT_EQUAL_64(0xfffffffffffe8fff, x7); in TEST()
107 ASSERT_EQUAL_64(0xf000100f, x8); in TEST()
108 ASSERT_EQUAL_64( in TEST()
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H A Dtest-assembler-fp-aarch64.cc79 ASSERT_EQUAL_64(src_base, x17); in TEST()
80 ASSERT_EQUAL_64(dst_base + sizeof(dst[0]), x18); in TEST()
81 ASSERT_EQUAL_64(src_base + sizeof(src[0]), x19); in TEST()
82 ASSERT_EQUAL_64(dst_base + 2 * sizeof(dst[0]), x20); in TEST()
83 ASSERT_EQUAL_64(src_base + 2 * sizeof(src[0]), x21); in TEST()
84 ASSERT_EQUAL_64(dst_base, x22); in TEST()
121 ASSERT_EQUAL_64(src_base, x17); in TEST()
122 ASSERT_EQUAL_64(dst_base + sizeof(dst[0]), x18); in TEST()
123 ASSERT_EQUAL_64(src_base + sizeof(src[0]), x19); in TEST()
124 ASSERT_EQUAL_64(dst_bas in TEST()
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H A Dtest-assembler-sve-aarch64.cc551 ASSERT_EQUAL_64(0x0000000000000010, x1);
552 ASSERT_EQUAL_64(0x0000000000000011, x3);
553 ASSERT_EQUAL_64(0x0000000000000010, x4);
554 ASSERT_EQUAL_64(0x0000000000000019, x5);
555 ASSERT_EQUAL_64(0x0000000000000018, x6);
556 ASSERT_EQUAL_64(0x0000000000000010, x7);
557 ASSERT_EQUAL_64(0x0000000000001110, x9);
558 ASSERT_EQUAL_64(0x0000000000001110, x12);
559 ASSERT_EQUAL_64(0x0000000011111111, x14);
560 ASSERT_EQUAL_64(
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H A Dtest-simulator-sve2-aarch64.cc191 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
335 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
479 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
623 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
867 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
1111 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
1255 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
1399 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
1543 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
1715 ASSERT_EQUAL_64(expected_hashe in TEST_SVE()
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H A Dtest-assembler-neon-aarch64.cc74 ASSERT_EQUAL_64(0x23, dst[0]); in TEST()
76 ASSERT_EQUAL_64(0x12, dst[2]); in TEST()
78 ASSERT_EQUAL_64(0x34, dst[1]); in TEST()
79 ASSERT_EQUAL_64(src_base, x17); in TEST()
80 ASSERT_EQUAL_64(dst_base + sizeof(dst[0]), x18); in TEST()
81 ASSERT_EQUAL_64(src_base + sizeof(src[0]), x19); in TEST()
82 ASSERT_EQUAL_64(dst_base + 2 * sizeof(dst[0]), x20); in TEST()
83 ASSERT_EQUAL_64(src_base + 2 * sizeof(src[0]), x21); in TEST()
84 ASSERT_EQUAL_64(dst_base, x22); in TEST()
116 ASSERT_EQUAL_64( in TEST()
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H A Dtest-simulator-sve-aarch64.cc182 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
266 ASSERT_EQUAL_64(expected_hashes[core.GetSVELaneCount(kQRegSize) - 1], x0); in TEST_SVE()
H A Dtest-assembler-aarch64.h42 // ASSERT_EQUAL_64(1, x0);
64 // ASSERT_EQUAL_64(int64_t, int_64t)
66 // ASSERT_EQUAL_64(int64_t, X register)
67 // ASSERT_EQUAL_64(X register, X register)
70 // e.g. ASSERT_EQUAL_64(0.5, d30);
75 // ASSERT_EQUAL_64(0x1234, core->reg_x0() & 0xffff);
317 #define ASSERT_EQUAL_64(expected, result) \ macro
/third_party/vixl/test/aarch32/
H A Dtest-assembler-aarch32.cc182 #define ASSERT_EQUAL_64(expected, result) macro
197 #define ASSERT_EQUAL_64(expected, result) \

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