Searched refs:ANDS (Results 1 - 14 of 14) sorted by relevance
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | constants-arm64.h | 601 ANDS = 0x60000000,
602 BICS = ANDS | NOT
616 ANDS_w_imm = LogicalImmediateFixed | ANDS,
617 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
643 ANDS_w = LogicalShiftedFixed | ANDS,
644 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
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| H A D | instructions-arm64.h | 270 // Of the logical (immediate) instructions, only ANDS (and its aliases) in RdMode()
274 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) { in RdMode()
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| H A D | macro-assembler-arm64-inl.h | 35 LogicalMacro(rd, rn, operand, ANDS); in Ands()
40 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS); in Tst() local
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| H A D | macro-assembler-arm64.cc | 195 case ANDS: // Fall through. in LogicalMacro()
213 case ANDS: // Fall through. in LogicalMacro()
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| H A D | assembler-arm64.cc | 916 Logical(rd, rn, operand, ANDS); in ands()
3767 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd); in LogicalImmediate()
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| /third_party/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 753 ANDS = 0x60000000, enumerator
754 BICS = ANDS | NOT
768 ANDS_w_imm = LogicalImmediateFixed | ANDS,
769 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
795 ANDS_w = LogicalShiftedFixed | ANDS,
796 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
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| H A D | instructions-aarch64.h | 610 // Of the logical (immediate) instructions, only ANDS (and its aliases) in GetRdMode()
614 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) { in GetRdMode()
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| H A D | macro-assembler-aarch64.cc | 812 LogicalMacro(rd, rn, operand, ANDS); in Emit()
918 case ANDS: in Emit()
937 case ANDS: in Emit()
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| H A D | assembler-aarch64.cc | 592 Logical(rd, rn, operand, ANDS); in ands()
6088 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd);
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| H A D | simulator-aarch64.cc | 4040 case ANDS: in Simulator()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 60 ANDS,
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| H A D | AArch64ISelLowering.cpp | 1255 case AArch64ISD::ANDS: return "AArch64ISD::ANDS"; in getTargetNodeName()
1740 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one in emitComparison()
1742 Opcode = AArch64ISD::ANDS; in emitComparison()
5037 // Don't combine AND since emitComparison converts the AND to an ANDS in LowerBR_CC()
5047 // Don't combine AND since emitComparison converts the AND to an ANDS in LowerBR_CC()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeARM_T2_32.c | 109 #define ANDS 0x4000 macro
881 return push_inst16(compiler, ANDS | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 1898 case ANDS:
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