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Searched refs:AH (Results 1 - 22 of 22) sorted by relevance

/third_party/node/deps/openssl/openssl/crypto/sha/asm/
H A Dsha256-586.pl376 my @AH=($A,$K256);
381 &mov ($AH[0],&DWP(0,"esi"));
382 &mov ($AH[1],&DWP(4,"esi"));
385 #&mov (&DWP(0,"esp"),$AH[0]);
386 &mov (&DWP(4,"esp"),$AH[1]);
387 &xor ($AH[1],"ecx"); # magic
459 &mov ($t1,$AH[0]);
463 &mov ($t2,$AH[0]);
465 &xor ($t1,$AH[0]);
466 &mov (&off($a),$AH[
[all...]
/third_party/openssl/crypto/sha/asm/
H A Dsha256-586.pl376 my @AH=($A,$K256);
381 &mov ($AH[0],&DWP(0,"esi"));
382 &mov ($AH[1],&DWP(4,"esi"));
385 #&mov (&DWP(0,"esp"),$AH[0]);
386 &mov (&DWP(4,"esp"),$AH[1]);
387 &xor ($AH[1],"ecx"); # magic
459 &mov ($t1,$AH[0]);
463 &mov ($t2,$AH[0]);
465 &xor ($t1,$AH[0]);
466 &mov (&off($a),$AH[
[all...]
/third_party/ffmpeg/libavcodec/
H A Dcavsdsp.c345 #define CAVS_SUBPIX_HV(OPNAME, OP, NAME, AH, BH, CH, DH, EH, FH, AV, BV, CV, DV, EV, FV, FULL) \
357 tmp[0]= AH*src1[-2] + BH*src1[-1] + CH*src1[0] + DH*src1[1] + EH*src1[2] + FH*src1[3];\
358 tmp[1]= AH*src1[-1] + BH*src1[ 0] + CH*src1[1] + DH*src1[2] + EH*src1[3] + FH*src1[4];\
359 tmp[2]= AH*src1[ 0] + BH*src1[ 1] + CH*src1[2] + DH*src1[3] + EH*src1[4] + FH*src1[5];\
360 tmp[3]= AH*src1[ 1] + BH*src1[ 2] + CH*src1[3] + DH*src1[4] + EH*src1[5] + FH*src1[6];\
361 tmp[4]= AH*src1[ 2] + BH*src1[ 3] + CH*src1[4] + DH*src1[5] + EH*src1[6] + FH*src1[7];\
362 tmp[5]= AH*src1[ 3] + BH*src1[ 4] + CH*src1[5] + DH*src1[6] + EH*src1[7] + FH*src1[8];\
363 tmp[6]= AH*src1[ 4] + BH*src1[ 5] + CH*src1[6] + DH*src1[7] + EH*src1[8] + FH*src1[9];\
364 tmp[7]= AH*src1[ 5] + BH*src1[ 6] + CH*src1[7] + DH*src1[8] + EH*src1[9] + FH*src1[10];\
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp93 {codeview::RegisterId::AH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
615 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
616 return X86::AH; in getX86SubSuperRegisterOrZero()
627 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
664 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
700 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
736 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
H A DX86MCCodeEmitter.cpp1190 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH) in determineREXPrefix()
/third_party/ltp/tools/sparse/sparse-src/
H A Dcompile-i386.c203 AL, DL, CL, BL, AH, DH, CH, BH, // 8-bit enumerator
221 REGINFO( AH, "%ah", AX, EAX, EAX_EDX),
225 REGINFO( AX, "%ax", AL, AH, EAX, EAX_EDX),
233 REGINFO(EAX, "%eax", AL, AH, AX, EAX_EDX),
241 REGINFO(EAX_EDX, "%eax:%edx", AL, AH, AX, EAX, DL, DH, DX, EDX),
250 REGSTORAGE(AH), REGSTORAGE(DH), REGSTORAGE(CH), REGSTORAGE(BH),
311 static struct regclass regclass_8 = { "8-bit", { AL, DL, CL, BL, AH, DH, CH, BH }};
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
H A DRewriteStatepointsForGC.cpp2384 static void RemoveNonValidAttrAtIndex(LLVMContext &Ctx, AttrHolder &AH, in RemoveNonValidAttrAtIndex() argument
2387 if (AH.getDereferenceableBytes(Index)) in RemoveNonValidAttrAtIndex()
2389 AH.getDereferenceableBytes(Index))); in RemoveNonValidAttrAtIndex()
2390 if (AH.getDereferenceableOrNullBytes(Index)) in RemoveNonValidAttrAtIndex()
2392 AH.getDereferenceableOrNullBytes(Index))); in RemoveNonValidAttrAtIndex()
2393 if (AH.getAttributes().hasAttribute(Index, Attribute::NoAlias)) in RemoveNonValidAttrAtIndex()
2397 AH.setAttributes(AH.getAttributes().removeAttributes(Ctx, Index, R)); in RemoveNonValidAttrAtIndex()
/third_party/rust/crates/rustix/src/backend/linux_raw/net/
H A Dtypes.rs184 pub const AH: Self = Self(c::IPPROTO_AH as _); consts
/third_party/lzma/Asm/x86/
H A D7zAsm.asm119 x0_H equ AH
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h83 ENTRY(AH) \
/third_party/rust/crates/rustix/src/backend/libc/net/
H A Dtypes.rs502 pub const AH: Self = Self(c::IPPROTO_AH as _); consts
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp1573 {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S}, // SRem in selectDivRem()
1575 {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U}, // URem in selectDivRem()
1690 OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) { in selectDivRem()
1696 // Shift AX right by 8 bits instead of using AH. in selectDivRem()
H A DX86FastISel.cpp1882 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem in X86SelectDivRem()
1884 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem in X86SelectDivRem()
1988 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()
1994 // Shift AX right by 8 bits instead of using AH. in X86SelectDivRem()
H A DX86ISelDAGToDAG.cpp3559 // Don't interfere with something that can be handled by extracting AH. in matchBEXTRFromAndImm()
3560 // TODO: If we are able to fold a load, BEXTR might still be better than AH. in matchBEXTRFromAndImm()
4890 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
4915 // clear the upper 8 bits (AH). in Select()
4991 // Prevent use of AH in a REX instruction by explicitly copying it to in Select()
4998 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) { in Select()
4999 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8); in Select()
H A DX86FrameLowering.cpp201 Reg == X86::AH || Reg == X86::AL) in isEAXLiveIn()
/third_party/node/deps/v8/src/execution/s390/
H A Dsimulator-s390.h552 EVALUATE(AH);
H A Dsimulator-s390.cc881 EvalTable[AH] = &Simulator::Evaluate_AH; in EvalTableInit()
5351 EVALUATE(AH) { in EVALUATE()
5352 DCHECK_OPCODE(AH); in EVALUATE()
/third_party/mesa3d/src/mesa/x86/
H A Dassyntax.h94 #define AH ah macro
156 #define AH %ah macro
819 #define B_AH AH
/third_party/node/deps/v8/src/codegen/s390/
H A Dconstants-s390.h1111 V(ah, AH, 0x4A) /* type = RX_A ADD HALFWORD (32<-16) */ \
/third_party/vixl/src/aarch64/
H A Dconstants-aarch64.h1349 N##AH = AtomicMemoryFixed | OP | 0x40800000, \
H A Dassembler-aarch64.cc1744 V(NAME##ah, OP##AH, OP##AH) \
H A Dsimulator-aarch64.cc5073 case A##AH: \ in Simulator()

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