| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64ExternalSymbolizer.cpp | 108 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
117 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| H A D | LoopRerollPass.cpp | 892 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(DRS.BaseInst)); in validateRootSet() local
893 if (!ADR) in validateRootSet()
898 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(DRS.Roots[0]), ADR); in validateRootSet()
900 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) in validateRootSet()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64MacroFusion.cpp | 219 case AArch64::ADR: in isAddressLdStPair()
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| H A D | AArch64ISelLowering.h | 37 ADR, // ADR
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| H A D | AArch64AsmPrinter.cpp | 841 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADR) in LowerJumpTableDestSmall()
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| H A D | AArch64ISelDAGToDAG.cpp | 2772 AArch64::ADR, DL, N->getSimpleValueType(0), MVT::Other, in tryReadRegister()
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| H A D | AArch64InstructionSelector.cpp | 1800 I.setDesc(TII.get(AArch64::ADR)); in select()
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| H A D | AArch64InstrInfo.cpp | 1548 BuildMI(MBB, MI, DL, get(AArch64::ADR), Reg) in expandPostRAPseudo()
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| H A D | AArch64ISelLowering.cpp | 1237 case AArch64ISD::ADR: return "AArch64ISD::ADR"; in getTargetNodeName()
4547 return DAG.getNode(AArch64ISD::ADR, DL, Ty, Sym); in getAddrTiny()
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| /third_party/vixl/src/aarch64/ |
| H A D | instructions-aarch64.cc | 903 // ADR and ADRP. in GetImmPCOffsetTarget()
909 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR); in GetImmPCOffsetTarget()
949 if ((Mask(PCRelAddressingMask) == ADR)) { in SetPCRelImmTarget()
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| H A D | constants-aarch64.h | 581 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
654 ADR = PCRelAddressingFixed | 0x00000000, enumerator
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| H A D | disasm-aarch64.cc | 1256 case ADR: in Disassembler()
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| H A D | assembler-aarch64.cc | 449 Emit(ADR | ImmPCRelAddress(imm21) | Rd(xd)); in adr()
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| H A D | simulator-aarch64.cc | 3713 VIXL_ASSERT((instr->Mask(PCRelAddressingMask) == ADR) || in Simulator()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | instructions-arm64.h | 218 bool IsAdr() const { return Mask(PCRelAddressingMask) == ADR; } in IsAdr()
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| H A D | constants-arm64.h | 460 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
524 ADR = PCRelAddressingFixed | 0x00000000,
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| H A D | assembler-arm64.cc | 620 // could be useful for ADR, for example.) in LinkAndGetByteOffsetTo()
660 // ADR instructions are not handled by veneers. in DeleteUnresolvedBranchInfoForLabelTraverse()
826 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 74 /// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
230 /// getAdrLabelOpValue - Return encoding info for 21-bit immediate ADR label
244 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR in getAdrLabelOpValue()
373 assert(MO.isExpr() && "Unexpected ADR target type!"); in getTestBranchTargetOpValue()
395 assert(MO.isExpr() && "Unexpected ADR target type!"); in getBranchTargetOpValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 1284 : ARM::ADR))
1300 : ARM::ADR))
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| /third_party/node/deps/v8/src/diagnostics/arm64/ |
| H A D | disasm-arm64.cc | 555 case ADR: in VisitPCRelAddressing()
4162 // Only ADR (AddrPCRelByte) is supported. in SubstitutePCRelAddressField()
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| /third_party/node/deps/v8/src/codegen/s390/ |
| H A D | constants-s390.h | 1509 V(adr, ADR, 0x2A) /* type = RR ADD NORMALIZED (long HFP) */ \
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 1687 case ADR:
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6555 // alternate form of ADR, which uses encoding T4, so check for that too. in shouldOmitCCOutOperand()
8306 // Alias for alternate form of 'ADR Rd, #imm' instruction. in processInstruction()
8313 TmpInst.setOpcode(ARM::ADR); in processInstruction()
8317 // before passing it to the ADR instruction. in processInstruction()
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