Searched refs:ADD_D (Results 1 - 12 of 12) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 421 ADD_D = 4, enumerator
703 return Latency::MUL_D + Latency::ADD_D; in MaddSLatency()
711 return Latency::MUL_D + Latency::ADD_D; in MaddDLatency()
781 Latency::ADD_D + Latency::CVT_D_W; in CvtDUwLatency()
1770 return Latency::ADD_D; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | instruction-scheduler-riscv64.cc | 449 ADD_D = 4, enumerator
1318 return Latency::ADD_D; in GetInstructionLatency()
1376 2 * Latency::CVT_D_L + Latency::ADD_D; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 448 ADD_D = 4, enumerator
1514 return Latency::ADD_D; in GetInstructionLatency()
1572 2 * Latency::CVT_D_L + Latency::ADD_D; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| H A D | constants-loong64.h | 335 ADD_D = 0x21U << 15,
1073 case ADD_D:
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| H A D | assembler-loong64.cc | 1029 GenRegister(ADD_D, rk, rj, rd); in add_d()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 682 ADD_D = ((0U << 3) + 0),
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| H A D | assembler-mips64.cc | 2804 GenInstrRegister(COP1, S, ft, fs, fd, ADD_D); in add_s()
2808 GenInstrRegister(COP1, D, ft, fs, fd, ADD_D); in add_d()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 637 ADD_D = ((0U << 3) + 0),
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| H A D | assembler-mips.cc | 2537 GenInstrRegister(COP1, D, ft, fs, fd, ADD_D); in add_d()
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| /third_party/node/deps/v8/src/execution/loong64/ |
| H A D | simulator-loong64.cc | 3450 case ADD_D:
3451 printf_instr("ADD_D\t %s: %016lx, %s, %016lx, %s, %016lx\n",
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 3167 case ADD_D: in DecodeTypeRegisterDRsType()
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 2786 case ADD_D: in DecodeTypeRegisterDRsType()
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