/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_vbif.c | 56 u32 xin_id, u32 value) in dpu_hw_set_mem_type() 67 if (!vbif || xin_id >= MAX_XIN_COUNT || xin_id >= 16) in dpu_hw_set_mem_type() 72 if (xin_id >= 8) { in dpu_hw_set_mem_type() 73 xin_id -= 8; in dpu_hw_set_mem_type() 78 bit_off = (xin_id & 0x7) * 4; in dpu_hw_set_mem_type() 86 u32 xin_id, bool rd, u32 limit) in dpu_hw_set_limit_conf() 98 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf() 99 bit_off = (xin_id % 4) * 8; in dpu_hw_set_limit_conf() 107 u32 xin_id, boo in dpu_hw_get_limit_conf() 55 dpu_hw_set_mem_type(struct dpu_hw_vbif *vbif, u32 xin_id, u32 value) dpu_hw_set_mem_type() argument 85 dpu_hw_set_limit_conf(struct dpu_hw_vbif *vbif, u32 xin_id, bool rd, u32 limit) dpu_hw_set_limit_conf() argument 106 dpu_hw_get_limit_conf(struct dpu_hw_vbif *vbif, u32 xin_id, bool rd) dpu_hw_get_limit_conf() argument 128 dpu_hw_set_halt_ctrl(struct dpu_hw_vbif *vbif, u32 xin_id, bool enable) dpu_hw_set_halt_ctrl() argument 144 dpu_hw_get_halt_ctrl(struct dpu_hw_vbif *vbif, u32 xin_id) dpu_hw_get_halt_ctrl() argument 155 dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif, u32 xin_id, u32 level, u32 remap_level) dpu_hw_set_qos_remap() argument 185 dpu_hw_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id) dpu_hw_set_write_gather_en() argument [all...] |
H A D | dpu_hw_vbif.h | 22 * @xin_id: client interface identifier 27 u32 xin_id, bool rd, u32 limit); 32 * @xin_id: client interface identifier 37 u32 xin_id, bool rd); 42 * @xin_id: client interface identifier 46 u32 xin_id, bool enable); 51 * @xin_id: client interface identifier 55 u32 xin_id); 60 * @xin_id: client interface identifier 65 u32 xin_id, u3 [all...] |
H A D | dpu_vbif.c | 37 * @xin_id: Client interface identifier 40 static int _dpu_vbif_wait_for_xin_halt(struct dpu_hw_vbif *vbif, u32 xin_id) in _dpu_vbif_wait_for_xin_halt() argument 53 status = vbif->ops.get_halt_ctrl(vbif, xin_id); in _dpu_vbif_wait_for_xin_halt() 57 status = vbif->ops.get_halt_ctrl(vbif, xin_id); in _dpu_vbif_wait_for_xin_halt() 66 dpu_vbif_name(vbif->idx), xin_id); in _dpu_vbif_wait_for_xin_halt() 70 dpu_vbif_name(vbif->idx), xin_id); in _dpu_vbif_wait_for_xin_halt() 111 dpu_vbif_name(vbif->idx), params->xin_id, in _dpu_vbif_apply_dynamic_ot_limit() 150 params->xin_id, params->rd); in _dpu_vbif_get_ot_limit() 157 dpu_vbif_name(vbif->idx), params->xin_id, ot_lim); in _dpu_vbif_get_ot_limit() 193 vbif->ops.set_write_gather_en(vbif, params->xin_id); in dpu_vbif_set_ot_limit() [all...] |
H A D | dpu_vbif.h | 11 u32 xin_id; member 23 u32 xin_id; member 32 * @xin_id: client interface identifier 39 u32 xin_id; member
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H A D | dpu_trace.h | 75 TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx), 76 TP_ARGS(pnum, xin_id, rd_lim, vbif_idx), 79 __field(u32, xin_id) 85 __entry->xin_id = xin_id; 89 TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d", 90 __entry->pnum, __entry->xin_id, __entry->rd_lim, 824 TP_PROTO(enum dpu_vbif index, u32 xin_id), 825 TP_ARGS(index, xin_id), 828 __field( u32, xin_id ) [all...] |
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_vbif.c | 56 u32 xin_id, u32 value) in dpu_hw_set_mem_type() 67 if (!vbif || xin_id >= MAX_XIN_COUNT || xin_id >= 16) in dpu_hw_set_mem_type() 72 if (xin_id >= 8) { in dpu_hw_set_mem_type() 73 xin_id -= 8; in dpu_hw_set_mem_type() 78 bit_off = (xin_id & 0x7) * 4; in dpu_hw_set_mem_type() 86 u32 xin_id, bool rd, u32 limit) in dpu_hw_set_limit_conf() 98 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf() 99 bit_off = (xin_id % 4) * 8; in dpu_hw_set_limit_conf() 107 u32 xin_id, boo in dpu_hw_get_limit_conf() 55 dpu_hw_set_mem_type(struct dpu_hw_vbif *vbif, u32 xin_id, u32 value) dpu_hw_set_mem_type() argument 85 dpu_hw_set_limit_conf(struct dpu_hw_vbif *vbif, u32 xin_id, bool rd, u32 limit) dpu_hw_set_limit_conf() argument 106 dpu_hw_get_limit_conf(struct dpu_hw_vbif *vbif, u32 xin_id, bool rd) dpu_hw_get_limit_conf() argument 128 dpu_hw_set_halt_ctrl(struct dpu_hw_vbif *vbif, u32 xin_id, bool enable) dpu_hw_set_halt_ctrl() argument 144 dpu_hw_get_halt_ctrl(struct dpu_hw_vbif *vbif, u32 xin_id) dpu_hw_get_halt_ctrl() argument 155 dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif, u32 xin_id, u32 level, u32 remap_level) dpu_hw_set_qos_remap() argument 184 dpu_hw_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id) dpu_hw_set_write_gather_en() argument [all...] |
H A D | dpu_hw_vbif.h | 22 * @xin_id: client interface identifier 27 u32 xin_id, bool rd, u32 limit); 32 * @xin_id: client interface identifier 37 u32 xin_id, bool rd); 42 * @xin_id: client interface identifier 46 u32 xin_id, bool enable); 51 * @xin_id: client interface identifier 55 u32 xin_id); 60 * @xin_id: client interface identifier 65 u32 xin_id, u3 [all...] |
H A D | dpu_vbif.c | 25 * @xin_id: Client interface identifier 28 static int _dpu_vbif_wait_for_xin_halt(struct dpu_hw_vbif *vbif, u32 xin_id) in _dpu_vbif_wait_for_xin_halt() argument 41 status = vbif->ops.get_halt_ctrl(vbif, xin_id); in _dpu_vbif_wait_for_xin_halt() 45 status = vbif->ops.get_halt_ctrl(vbif, xin_id); in _dpu_vbif_wait_for_xin_halt() 54 vbif->idx - VBIF_0, xin_id); in _dpu_vbif_wait_for_xin_halt() 58 vbif->idx - VBIF_0, xin_id); in _dpu_vbif_wait_for_xin_halt() 99 vbif->idx - VBIF_0, params->xin_id, in _dpu_vbif_apply_dynamic_ot_limit() 138 params->xin_id, params->rd); in _dpu_vbif_get_ot_limit() 145 vbif->idx - VBIF_0, params->xin_id, ot_lim); in _dpu_vbif_get_ot_limit() 181 vbif->ops.set_write_gather_en(vbif, params->xin_id); in dpu_vbif_set_ot_limit() [all...] |
H A D | dpu_vbif.h | 11 u32 xin_id; member 23 u32 xin_id; member 32 * @xin_id: client interface identifier 39 u32 xin_id; member
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H A D | dpu_trace.h | 75 TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx), 76 TP_ARGS(pnum, xin_id, rd_lim, vbif_idx), 79 __field(u32, xin_id) 85 __entry->xin_id = xin_id; 89 TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d", 90 __entry->pnum, __entry->xin_id, __entry->rd_lim, 855 TP_PROTO(enum dpu_vbif index, u32 xin_id), 856 TP_ARGS(index, xin_id), 859 __field( u32, xin_id ) [all...] |
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
H A D | dpu_3_0_msm8998.h | 74 .xin_id = 0, 82 .xin_id = 4, 90 .xin_id = 8, 98 .xin_id = 12, 106 .xin_id = 1, 114 .xin_id = 5, 122 .xin_id = 9, 130 .xin_id = 13,
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H A D | dpu_9_0_sm8550.h | 82 .xin_id = 0, 90 .xin_id = 4, 98 .xin_id = 8, 106 .xin_id = 12, 114 .xin_id = 1, 122 .xin_id = 5, 130 .xin_id = 9, 138 .xin_id = 13, 146 .xin_id = 14, 154 .xin_id [all...] |
H A D | dpu_7_0_sm8350.h | 80 .xin_id = 0, 88 .xin_id = 4, 96 .xin_id = 8, 104 .xin_id = 12, 112 .xin_id = 1, 120 .xin_id = 5, 128 .xin_id = 9, 136 .xin_id = 13, 316 .xin_id = 6,
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H A D | dpu_6_0_sm8250.h | 80 .xin_id = 0, 88 .xin_id = 4, 96 .xin_id = 8, 104 .xin_id = 12, 112 .xin_id = 1, 120 .xin_id = 5, 128 .xin_id = 9, 136 .xin_id = 13, 351 .xin_id = 6,
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H A D | dpu_8_1_sm8450.h | 81 .xin_id = 0, 89 .xin_id = 4, 97 .xin_id = 8, 105 .xin_id = 12, 113 .xin_id = 1, 121 .xin_id = 5, 129 .xin_id = 9, 137 .xin_id = 13, 338 .xin_id = 6,
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H A D | dpu_6_2_sc7180.h | 57 .xin_id = 0, 65 .xin_id = 1, 73 .xin_id = 5, 81 .xin_id = 9, 167 .xin_id = 6,
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H A D | dpu_5_1_sc8180x.h | 80 .xin_id = 0, 88 .xin_id = 4, 96 .xin_id = 8, 104 .xin_id = 12, 112 .xin_id = 1, 120 .xin_id = 5, 128 .xin_id = 9, 136 .xin_id = 13,
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H A D | dpu_8_0_sc8280xp.h | 80 .xin_id = 0, 88 .xin_id = 4, 96 .xin_id = 8, 104 .xin_id = 12, 112 .xin_id = 1, 120 .xin_id = 5, 128 .xin_id = 9, 136 .xin_id = 13,
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H A D | dpu_5_0_sm8150.h | 81 .xin_id = 0, 89 .xin_id = 4, 97 .xin_id = 8, 105 .xin_id = 12, 113 .xin_id = 1, 121 .xin_id = 5, 129 .xin_id = 9, 137 .xin_id = 13,
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H A D | dpu_4_0_sdm845.h | 72 .xin_id = 0, 80 .xin_id = 4, 88 .xin_id = 8, 96 .xin_id = 12, 104 .xin_id = 1, 112 .xin_id = 5, 120 .xin_id = 9, 128 .xin_id = 13,
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H A D | dpu_6_4_sm6350.h | 64 .xin_id = 0, 72 .xin_id = 1, 80 .xin_id = 5, 88 .xin_id = 9,
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H A D | dpu_7_2_sc7280.h | 62 .xin_id = 0, 70 .xin_id = 1, 78 .xin_id = 5, 86 .xin_id = 9, 180 .xin_id = 6,
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H A D | dpu_5_4_sm6125.h | 73 .xin_id = 0, 81 .xin_id = 1, 89 .xin_id = 5,
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H A D | dpu_6_3_sm6115.h | 44 .xin_id = 0, 52 .xin_id = 1,
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H A D | dpu_6_5_qcm2290.h | 43 .xin_id = 0, 51 .xin_id = 1,
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