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Searched refs:xcc_mask (Results 1 - 25 of 25) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_2.c45 uint32_t xcc_mask) in gfxhub_v1_2_xcc_setup_vm_pt_regs()
50 for_each_inst(i, xcc_mask) { in gfxhub_v1_2_xcc_setup_vm_pt_regs()
68 uint32_t xcc_mask; in gfxhub_v1_2_setup_vm_pt_regs() local
70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_setup_vm_pt_regs()
71 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, xcc_mask); in gfxhub_v1_2_setup_vm_pt_regs()
75 uint32_t xcc_mask) in gfxhub_v1_2_xcc_init_gart_aperture_regs()
85 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
90 for_each_inst(i, xcc_mask) { in gfxhub_v1_2_xcc_init_gart_aperture_regs()
125 uint32_t xcc_mask) in gfxhub_v1_2_xcc_init_system_aperture_regs()
42 gfxhub_v1_2_xcc_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base, uint32_t xcc_mask) gfxhub_v1_2_xcc_setup_vm_pt_regs() argument
74 gfxhub_v1_2_xcc_init_gart_aperture_regs(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_init_gart_aperture_regs() argument
124 gfxhub_v1_2_xcc_init_system_aperture_regs(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_init_system_aperture_regs() argument
194 gfxhub_v1_2_xcc_init_tlb_regs(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_init_tlb_regs() argument
220 gfxhub_v1_2_xcc_init_cache_regs(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_init_cache_regs() argument
269 gfxhub_v1_2_xcc_enable_system_domain(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_enable_system_domain() argument
289 gfxhub_v1_2_xcc_disable_identity_aperture(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_disable_identity_aperture() argument
316 gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_setup_vmid_config() argument
386 gfxhub_v1_2_xcc_program_invalidation(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_program_invalidation() argument
404 gfxhub_v1_2_xcc_gart_enable(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_gart_enable() argument
425 uint32_t xcc_mask; gfxhub_v1_2_gart_enable() local
431 gfxhub_v1_2_xcc_gart_disable(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_gart_disable() argument
464 uint32_t xcc_mask; gfxhub_v1_2_gart_disable() local
470 gfxhub_v1_2_xcc_set_fault_enable_default(struct amdgpu_device *adev, bool value, uint32_t xcc_mask) gfxhub_v1_2_xcc_set_fault_enable_default() argument
522 uint32_t xcc_mask; gfxhub_v1_2_set_fault_enable_default() local
528 gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask) gfxhub_v1_2_xcc_init() argument
571 uint32_t xcc_mask; gfxhub_v1_2_init() local
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H A Daqua_vanjaram.c267 { GC_HWIP, adev->gfx.xcc_mask }, in aqua_vanjaram_ip_map_init()
314 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_xcc_per_xcp()
407 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); in __aqua_vanjaram_get_auto_mode()
431 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in __aqua_vanjaram_is_valid_mode()
492 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in aqua_vanjaram_switch_partition_mode()
548 uint32_t xcc_mask; in aqua_vanjaram_get_xcp_mem_id() local
565 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); in aqua_vanjaram_get_xcp_mem_id()
566 if (r || !xcc_mask) in aqua_vanjaram_get_xcp_mem_id()
569 xcc_id = ffs(xcc_mask) - 1; in aqua_vanjaram_get_xcp_mem_id()
H A Damdgpu_gfx.c214 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_compute_queue_acquire()
907 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_ras_error_func()
908 uint32_t xcc_mask = GENMASK(num_xcc - 1, 0); in amdgpu_gfx_ras_error_func() local
916 for_each_inst(i, xcc_mask) in amdgpu_gfx_ras_error_func()
1227 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gfx_set_compute_partition()
1272 switch (NUM_XCC(adev->gfx.xcc_mask)) { in amdgpu_gfx_get_available_compute_partition()
H A Dgfx_v9_4_3.c187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_set_kiq_pm4_funcs()
196 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_golden_registers()
461 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_mec_init()
630 NUM_XCC(adev->gfx.xcc_mask) / in gfx_v9_4_3_switch_compute_partition()
636 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_switch_compute_partition()
658 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); in gfx_v9_4_3_ih_to_xcc_inst()
788 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_init()
882 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_sw_fini()
1015 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_constants_init()
1094 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
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H A Dta_ras_if.h132 uint16_t xcc_mask; member
H A Dgmc_v9_0.c1886 uint32_t xcc_mask; in gmc_v9_0_init_acpi_mem_ranges() local
1888 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in gmc_v9_0_init_acpi_mem_ranges()
1889 xcc_mask = (1U << num_xcc) - 1; in gmc_v9_0_init_acpi_mem_ranges()
1892 for_each_inst(xcc_id, xcc_mask) { in gmc_v9_0_init_acpi_mem_ranges()
2113 NUM_XCC(adev->gfx.xcc_mask)); in gmc_v9_0_sw_init()
H A Damdgpu_gfx.h438 uint16_t xcc_mask; member
H A Dnbio_v7_9.c436 0xff & ~(adev->gfx.xcc_mask)); in nbio_v7_9_init_registers()
H A Damdgpu_discovery.c650 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
934 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1225 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1311 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
H A Damdgpu_virt.c996 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
H A Damdgpu_ras.c339 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_ras_instance_mask_check()
H A Damdgpu_psp.c1672 ras_cmd->ras_in_message.init_flags.xcc_mask = in psp_ras_initialize()
1673 adev->gfx.xcc_mask; in psp_ras_initialize()
H A Dgfx_v6_0.c3031 adev->gfx.xcc_mask = 1; in gfx_v6_0_early_init()
H A Dgfx_v7_0.c4179 adev->gfx.xcc_mask = 1; in gfx_v7_0_early_init()
H A Dgfx_v9_0.c4525 adev->gfx.xcc_mask = 1; in gfx_v9_0_early_init()
H A Dgfx_v8_0.c5265 adev->gfx.xcc_mask = 1; in gfx_v8_0_early_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c139 NUM_XCC(node->xcc_mask), in allocate_mqd()
530 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in init_mqd_hiq_v9_4_3()
554 uint32_t xcc_mask = mm->dev->xcc_mask; in hiq_load_mqd_kiq_v9_4_3() local
559 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
578 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_hiq_mqd_v9_4_3() local
584 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
625 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in init_mqd_v9_4_3()
652 NUM_XCC(mm->dev->xcc_mask); in init_mqd_v9_4_3()
715 uint32_t xcc_mask = mm->dev->xcc_mask; destroy_mqd_v9_4_3() local
745 uint32_t xcc_mask = mm->dev->xcc_mask; load_mqd_v9_4_3() local
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H A Dkfd_mqd_manager.c80 NUM_XCC(dev->xcc_mask); in allocate_sdma_mqd()
108 int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask); in mqd_symmetrically_map_cu_mask()
109 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; in mqd_symmetrically_map_cu_mask()
H A Dkfd_device_queue_manager.c143 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_sh_mem_settings() local
146 for_each_inst(xcc_id, xcc_mask) in program_sh_mem_settings()
433 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_trap_handler_settings() local
437 for_each_inst(xcc_id, xcc_mask) in program_trap_handler_settings()
703 uint32_t xcc_mask = dev->xcc_mask; in dbgdev_wave_reset_wavefronts() local
749 for_each_inst(xcc_id, xcc_mask) in dbgdev_wave_reset_wavefronts()
1364 uint32_t xcc_mask in set_pasid_vmid_mapping() local
1379 uint32_t xcc_mask = dqm->dev->xcc_mask; init_interrupts() local
3158 uint32_t xcc_mask = dqm->dev->xcc_mask; dqm_debugfs_hqds() local
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H A Dkfd_device.c596 uint32_t xcc_mask = node->xcc_mask; in kfd_setup_interrupt_bitmap() local
619 for_each_inst(xcc, xcc_mask) { in kfd_setup_interrupt_bitmap()
776 &node->xcc_mask); in kgd2kfd_device_init()
779 node->xcc_mask = in kgd2kfd_device_init()
780 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; in kgd2kfd_device_init()
H A Dkfd_topology.c478 NUM_XCC(dev->gpu->xcc_mask)) : 0); in node_show()
544 NUM_XCC(dev->gpu->xcc_mask)); in node_show()
1113 buf[7] = (ffs(gpu->xcc_mask) - 1) | (NUM_XCC(gpu->xcc_mask) << 16); in kfd_generate_gpu_id()
1612 start = ffs(knode->xcc_mask) - 1; in fill_in_l2_l3_pcache()
1613 end = start + NUM_XCC(knode->xcc_mask); in fill_in_l2_l3_pcache()
1712 start = ffs(kdev->xcc_mask) - 1; in kfd_fill_cache_non_crat_info()
1713 end = start + NUM_XCC(kdev->xcc_mask); in kfd_fill_cache_non_crat_info()
H A Dkfd_debug.c448 uint32_t xcc_mask = pdd->dev->xcc_mask; in kfd_dbg_trap_set_dev_address_watch() local
462 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
1066 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); in kfd_dbg_trap_device_snapshot()
H A Dkfd_process.c2062 uint32_t xcc_mask = dev->xcc_mask; in kfd_flush_tlb() local
2081 for_each_inst(xcc, xcc_mask) in kfd_flush_tlb()
H A Dkfd_priv.h270 uint32_t xcc_mask; /* Instance mask of XCCs present */ member
H A Dkfd_process_queue_manager.c1035 num_xccs = NUM_XCC(q->device->xcc_mask); in pqm_debugfs_mqds()

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