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/kernel/linux/linux-6.6/arch/s390/boot/
H A Dipl_data.c50 [ 0] = CCW0(CCW_CMD_READ_IPL, 0x018, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
51 [ 1] = CCW0(CCW_CMD_READ_IPL, 0x068, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
57 [ 0] = CCW0(CCW_CMD_READ_IPL, 0x0f0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
58 [ 1] = CCW0(CCW_CMD_READ_IPL, 0x140, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
59 [ 2] = CCW0(CCW_CMD_READ_IPL, 0x190, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
60 [ 3] = CCW0(CCW_CMD_READ_IPL, 0x1e0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
61 [ 4] = CCW0(CCW_CMD_READ_IPL, 0x230, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
62 [ 5] = CCW0(CCW_CMD_READ_IPL, 0x280, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
63 [ 6] = CCW0(CCW_CMD_READ_IPL, 0x2d0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC),
64 [ 7] = CCW0(CCW_CMD_READ_IPL, 0x320, 0x50, CCW_FLAG_SL
[all...]
/kernel/linux/linux-6.6/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7981.c167 PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
168 PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
169 PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
170 PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
171 PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
172 PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
173 PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
177 PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
178 PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
179 PIN_FIELD_BASE(42, 42, 7, 0x50,
[all...]
H A Dpinctrl-mt7986.c200 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
201 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
202 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
203 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
204 PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
205 PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
206 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
207 PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
208 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
209 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50,
[all...]
H A Dpinctrl-mt8173.c217 MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
268 MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
269 MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
270 MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
271 MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
272 MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
279 MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
280 MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
281 MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
282 MTK_PIN_DRV_GRP(122, DRV_BASE+0x50,
[all...]
H A Dpinctrl-mt8135.c145 MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
146 MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
147 MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
148 MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
149 MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
150 MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
151 MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
155 MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
156 MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
157 MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 2
[all...]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
H A Dmb86a20s.c62 { 0x50, 0xd1 }, { 0x51, 0x20 },
66 { 0x50, 0xd1 }, { 0x51, 0x22 },
103 { 0x50, 0xa7 }, { 0x51, 0x00 },
104 { 0x50, 0xa8 }, { 0x51, 0xff },
105 { 0x50, 0xa9 }, { 0x51, 0xff },
106 { 0x50, 0xaa }, { 0x51, 0x00 },
107 { 0x50, 0xab }, { 0x51, 0xff },
108 { 0x50, 0xac }, { 0x51, 0xff },
109 { 0x50, 0xad }, { 0x51, 0x00 },
110 { 0x50,
[all...]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
H A Dmb86a20s.c62 { 0x50, 0xd1 }, { 0x51, 0x20 },
66 { 0x50, 0xd1 }, { 0x51, 0x22 },
103 { 0x50, 0xa7 }, { 0x51, 0x00 },
104 { 0x50, 0xa8 }, { 0x51, 0xff },
105 { 0x50, 0xa9 }, { 0x51, 0xff },
106 { 0x50, 0xaa }, { 0x51, 0x00 },
107 { 0x50, 0xab }, { 0x51, 0xff },
108 { 0x50, 0xac }, { 0x51, 0xff },
109 { 0x50, 0xad }, { 0x51, 0x00 },
110 { 0x50,
[all...]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-loongson2ef/cs5536/
H A Dcs5536_pci.h120 #define PCI_UART1_INT_REG 0x50
131 #define PCI_IDE_ETC_REG 0x50
138 #define PCI_ACC_INT_REG 0x50
144 #define PCI_OHCI_INT_REG 0x50
149 #define PCI_EHCI_LEGSMIEN_REG 0x50
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-loongson2ef/cs5536/
H A Dcs5536_pci.h120 #define PCI_UART1_INT_REG 0x50
131 #define PCI_IDE_ETC_REG 0x50
138 #define PCI_ACC_INT_REG 0x50
144 #define PCI_OHCI_INT_REG 0x50
149 #define PCI_EHCI_LEGSMIEN_REG 0x50
/kernel/linux/linux-6.6/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt36672a.c282 { .data = {0x11, 0x50} },
338 { .data = {0x50, 0x40} },
348 { .data = {0x5B, 0x50} },
349 { .data = {0x5C, 0x50} },
350 { .data = {0x5D, 0x50} },
351 { .data = {0x5E, 0x50} },
352 { .data = {0x5F, 0x50} },
353 { .data = {0x60, 0x50} },
354 { .data = {0x61, 0x50} },
355 { .data = {0x62, 0x50} },
[all...]
/kernel/linux/linux-5.10/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8173.c237 MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
288 MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
289 MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
290 MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
291 MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
292 MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
299 MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
300 MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
301 MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
302 MTK_PIN_DRV_GRP(122, DRV_BASE+0x50,
[all...]
H A Dpinctrl-mt8135.c146 MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
147 MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
148 MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
149 MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
150 MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
151 MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
152 MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
156 MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
157 MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
158 MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 2
[all...]
/kernel/linux/linux-5.10/drivers/media/tuners/
H A Dfc2580_priv.h99 0x50, 0x0f, 0x07, 0x00, 0x15, 0x03, 0x05, 0x10, 0x12, 0x08,
103 0x50, 0x13, 0x07, 0x06, 0x15, 0x06, 0x08, 0x10, 0x12, 0x0b,
107 0x50, 0x15, 0x03, 0x03, 0x15, 0x03, 0x05, 0x0c, 0x0e, 0x0b,
111 0x50, 0x15, 0x07, 0x06, 0x15, 0x07, 0x09, 0x10, 0x12, 0x0b,
115 0x50, 0x0f, 0x0f, 0x00, 0x13, 0x00, 0x02, 0x0c, 0x0e, 0x08,
116 0x0a, 0xa0, 0x50, 0x14},
/kernel/linux/linux-6.6/drivers/media/tuners/
H A Dfc2580_priv.h99 0x50, 0x0f, 0x07, 0x00, 0x15, 0x03, 0x05, 0x10, 0x12, 0x08,
103 0x50, 0x13, 0x07, 0x06, 0x15, 0x06, 0x08, 0x10, 0x12, 0x0b,
107 0x50, 0x15, 0x03, 0x03, 0x15, 0x03, 0x05, 0x0c, 0x0e, 0x0b,
111 0x50, 0x15, 0x07, 0x06, 0x15, 0x07, 0x09, 0x10, 0x12, 0x0b,
115 0x50, 0x0f, 0x0f, 0x00, 0x13, 0x00, 0x02, 0x0c, 0x0e, 0x08,
116 0x0a, 0xa0, 0x50, 0x14},
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.h97 #define DPCD_LTTPR_PATTERN_SET(i) ((i - 1) * 0x50 + 0xf0010)
98 #define DPCD_LTTPR_LANE0_SET(i) ((i - 1) * 0x50 + 0xf0011)
99 #define DPCD_LTTPR_AUX_RD_INTERVAL(i) ((i - 1) * 0x50 + 0xf0020)
100 #define DPCD_LTTPR_LANE0_1_STATUS(i) ((i - 1) * 0x50 + 0xf0030)
101 #define DPCD_LTTPR_LANE0_1_ADJUST(i) ((i - 1) * 0x50 + 0xf0033)
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv50.c308 if (device->chipset == 0x50) { in nv50_gr_construct_mmio()
319 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
356 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
366 if (device->chipset == 0x50) { in nv50_gr_construct_mmio()
380 case 0x50: in nv50_gr_construct_mmio()
408 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
416 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
421 if (device->chipset != 0x50) in nv50_gr_construct_mmio()
424 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
449 case 0x50 in nv50_gr_construct_mmio()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv50.c308 if (device->chipset == 0x50) { in nv50_gr_construct_mmio()
319 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
356 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
366 if (device->chipset == 0x50) { in nv50_gr_construct_mmio()
380 case 0x50: in nv50_gr_construct_mmio()
408 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
416 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
421 if (device->chipset != 0x50) in nv50_gr_construct_mmio()
424 if (device->chipset == 0x50) in nv50_gr_construct_mmio()
449 case 0x50 in nv50_gr_construct_mmio()
[all...]
/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Ddra7.h19 #define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
71 #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
99 #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
118 #define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50)
175 #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
192 #define DRA7_IPU_CLKCTRL_OFFSET 0x50
194 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
250 #define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
275 #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
300 #define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
[all...]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Ddra7.h19 #define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50)
71 #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
99 #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
118 #define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50)
175 #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
192 #define DRA7_IPU_CLKCTRL_OFFSET 0x50
194 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
250 #define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
275 #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
300 #define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
[all...]
/kernel/linux/linux-5.10/drivers/char/agp/
H A Dintel-agp.h12 #define INTEL_NBXCFG 0x50
55 #define INTEL_I860_MCHCFG 0x50
109 #define INTEL_I840_MCHCFG 0x50
113 #define INTEL_I850_MCHCFG 0x50
143 #define INTEL_I7505_MCHCFG 0x50
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Dauxgm200.c36 nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00710000, 0x00000000); in gm200_i2c_aux_fini()
51 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50)); in gm200_i2c_aux_init()
60 nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00700000, ureq); in gm200_i2c_aux_init()
63 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50)); in gm200_i2c_aux_init()
81 const u32 base = aux->ch * 0x50; in gm200_i2c_aux_xfer()
/kernel/linux/linux-6.6/drivers/char/agp/
H A Dintel-agp.h12 #define INTEL_NBXCFG 0x50
55 #define INTEL_I860_MCHCFG 0x50
109 #define INTEL_I840_MCHCFG 0x50
113 #define INTEL_I850_MCHCFG 0x50
143 #define INTEL_I7505_MCHCFG 0x50
/kernel/linux/linux-5.10/arch/sparc/include/uapi/asm/
H A Dptrace.h172 #define TRACEREG32_SZ 0x50
185 #define TRACEREG_SZ 0x50
203 #define PT_V9_I2 0x50
254 #define RW_V9_I2 0x50
289 #define SF_V9_I2 0x50
324 #define SF_XARG3 0x50
/kernel/linux/linux-6.6/arch/sparc/include/uapi/asm/
H A Dptrace.h172 #define TRACEREG32_SZ 0x50
185 #define TRACEREG_SZ 0x50
203 #define PT_V9_I2 0x50
254 #define RW_V9_I2 0x50
289 #define SF_V9_I2 0x50
324 #define SF_XARG3 0x50
/kernel/linux/linux-5.10/drivers/irqchip/
H A Dirq-renesas-h8s.c22 0x50, 0x50, 0x50, 0x50, 0x63, 0x63, 0x63, 0x63, /* 48 - 55 */

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