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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Drv770_smc.c199 0x0C, 0x14, 0x0C, 0x14,
200 0x0C, 0x14, 0x0C, 0x14,
201 0x0C, 0x14, 0x0C, 0x14,
202 0x0C, 0x14, 0x0C, 0x14,
203 0x0C, 0x14, 0x0C, 0x14,
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Drv770_smc.c190 0x0C, 0x14, 0x0C, 0x14,
191 0x0C, 0x14, 0x0C, 0x14,
192 0x0C, 0x14, 0x0C, 0x14,
193 0x0C, 0x14, 0x0C, 0x14,
194 0x0C, 0x14, 0x0C, 0x14,
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
89 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); in rtl8168h_config_eee_phy()
97 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); in rtl8125a_config_eee_phy()
103 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); in rtl8125b_config_eee_phy()
104 phy_modify_paged(phydev, 0xa42, 0x14, 0x0080, 0x0000); in rtl8125b_config_eee_phy()
216 { 0x14, 0xfb54 }, in rtl8169scd_hw_phy_config()
307 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168cp_2_hw_phy_config()
337 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_1_hw_phy_config()
365 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_2_hw_phy_config()
387 phy_set_bits(phydev, 0x14, BI in rtl8168c_3_hw_phy_config()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_4_0_sh_mask.h217 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
229 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
343 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
352 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
361 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
370 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
379 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
388 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
397 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
452 #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
[all...]
H A Dhdp_5_0_0_sh_mask.h167 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
274 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
286 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
400 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
409 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
418 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
427 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
436 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
445 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
454 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_4_0_sh_mask.h219 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
231 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
345 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
354 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
363 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
372 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
381 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
390 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
399 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
454 #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
[all...]
H A Dhdp_5_2_1_sh_mask.h124 #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14
155 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
251 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
263 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
377 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
386 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
395 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
404 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
413 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
422 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
[all...]
H A Dhdp_4_4_2_sh_mask.h126 #define HDP_MISC_CNTL__SRAM_ECC_ENABLE__SHIFT 0x14
161 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
268 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
280 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
394 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
403 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
412 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
421 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
430 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
439 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
[all...]
H A Dhdp_6_0_0_sh_mask.h105 #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14
133 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
229 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
241 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
355 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
364 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
373 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
382 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
391 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
400 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
[all...]
H A Dhdp_5_0_0_sh_mask.h167 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
274 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
286 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
400 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
409 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
418 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
427 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
436 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
445 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
454 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
[all...]
/kernel/linux/linux-5.10/arch/x86/kernel/
H A Dsignal_compat.c74 BUILD_BUG_ON(offsetof(siginfo_t, si_uid) != 0x14); in signal_compat_build_tests()
83 BUILD_BUG_ON(offsetof(siginfo_t, si_overrun) != 0x14); in signal_compat_build_tests()
87 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_value) != 0x14); in signal_compat_build_tests()
94 BUILD_BUG_ON(offsetof(siginfo_t, si_uid) != 0x14); in signal_compat_build_tests()
98 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_value) != 0x14); in signal_compat_build_tests()
105 BUILD_BUG_ON(offsetof(siginfo_t, si_uid) != 0x14); in signal_compat_build_tests()
111 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_status) != 0x14); in signal_compat_build_tests()
135 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_lower) != 0x14); in signal_compat_build_tests()
139 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_pkey) != 0x14); in signal_compat_build_tests()
159 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_arch) != 0x14); in signal_compat_build_tests()
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Dhardware.h125 #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
133 #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
141 #define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
149 #define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
157 #define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
165 #define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
173 #define IRQ_SIR_FIQ_REG_OFFSET 0x14
205 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
/kernel/linux/linux-5.10/include/linux/regulator/
H A Dpca9450.h70 PCA9450_REG_BUCK2OUT_DVS0 = 0x14,
155 #define BUCK1OUT_DVS0_DEFAULT 0x14
159 #define BUCK1OUT_DVS1_DEFAULT 0x14
163 #define BUCK2OUT_DVS0_DEFAULT 0x14
167 #define BUCK2OUT_DVS1_DEFAULT 0x14
171 #define BUCK3OUT_DVS0_DEFAULT 0x14
175 #define BUCK3OUT_DVS1_DEFAULT 0x14
187 #define BUCK6OUT_DEFAULT 0x14
/kernel/linux/linux-6.6/include/linux/regulator/
H A Dpca9450.h70 PCA9450_REG_BUCK2OUT_DVS0 = 0x14,
155 #define BUCK1OUT_DVS0_DEFAULT 0x14
159 #define BUCK1OUT_DVS1_DEFAULT 0x14
163 #define BUCK2OUT_DVS0_DEFAULT 0x14
167 #define BUCK2OUT_DVS1_DEFAULT 0x14
171 #define BUCK3OUT_DVS0_DEFAULT 0x14
175 #define BUCK3OUT_DVS1_DEFAULT 0x14
187 #define BUCK6OUT_DEFAULT 0x14
/kernel/linux/linux-5.10/drivers/hid/
H A Dhid-waltop.c62 0x14, /* Logical Minimum (0), */
71 0x14, /* Logical Minimum (0), */
113 0x14, /* Logical Minimum (0), */
122 0x14, /* Logical Minimum (0), */
164 0x14, /* Logical Minimum (0), */
173 0x14, /* Logical Minimum (0), */
217 0x14, /* Logical Minimum (0), */
226 0x14, /* Logical Minimum (0), */
237 0x46, 0x82, 0x14, /* Physical Maximum (5250), */
269 0x14, /* Logica
[all...]
/kernel/linux/linux-6.6/drivers/hid/
H A Dhid-waltop.c62 0x14, /* Logical Minimum (0), */
71 0x14, /* Logical Minimum (0), */
113 0x14, /* Logical Minimum (0), */
122 0x14, /* Logical Minimum (0), */
164 0x14, /* Logical Minimum (0), */
173 0x14, /* Logical Minimum (0), */
217 0x14, /* Logical Minimum (0), */
226 0x14, /* Logical Minimum (0), */
237 0x46, 0x82, 0x14, /* Physical Maximum (5250), */
269 0x14, /* Logica
[all...]
H A Dhid-uclogic-rdesc.c33 0x14, /* Logical Minimum (0), */
41 0x14, /* Logical Minimum (0), */
78 0x14, /* Logical Minimum (0), */
86 0x14, /* Logical Minimum (0), */
116 0x14, /* Logical Minimum (0), */
155 0x14, /* Logical Minimum (0), */
163 0x14, /* Logical Minimum (0), */
193 0x14, /* Logical Minimum (0), */
232 0x14, /* Logical Minimum (0), */
243 0x14, /* Logica
[all...]
/kernel/linux/linux-5.10/drivers/clk/bcm/
H A Dclk-ns2.c74 .mdiv = REG_VAL(0x14, 0, 8),
80 .mdiv = REG_VAL(0x14, 8, 8),
86 .mdiv = REG_VAL(0x14, 16, 8),
92 .mdiv = REG_VAL(0x14, 24, 8),
136 .mdiv = REG_VAL(0x14, 0, 8),
142 .mdiv = REG_VAL(0x14, 8, 8),
148 .mdiv = REG_VAL(0x14, 16, 8),
154 .mdiv = REG_VAL(0x14, 24, 8),
186 .mdiv = REG_VAL(0x14, 0, 8),
192 .mdiv = REG_VAL(0x14,
[all...]
/kernel/linux/linux-6.6/drivers/clk/bcm/
H A Dclk-ns2.c64 .mdiv = REG_VAL(0x14, 0, 8),
70 .mdiv = REG_VAL(0x14, 8, 8),
76 .mdiv = REG_VAL(0x14, 16, 8),
82 .mdiv = REG_VAL(0x14, 24, 8),
126 .mdiv = REG_VAL(0x14, 0, 8),
132 .mdiv = REG_VAL(0x14, 8, 8),
138 .mdiv = REG_VAL(0x14, 16, 8),
144 .mdiv = REG_VAL(0x14, 24, 8),
176 .mdiv = REG_VAL(0x14, 0, 8),
182 .mdiv = REG_VAL(0x14,
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_2_0_0_sh_mask.h42 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
67 #define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14
109 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
167 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14
193 #define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14
255 #define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14
332 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14
374 #define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14
410 #define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14
451 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14
[all...]
H A Ddpcs_3_0_0_sh_mask.h30 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
56 #define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14
86 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
145 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14
171 #define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14
206 #define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14
283 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14
325 #define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14
361 #define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14
402 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_2_0_0_sh_mask.h42 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
67 #define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14
109 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
167 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14
193 #define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14
255 #define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14
332 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14
374 #define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14
410 #define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14
451 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddpcs_3_0_0_sh_mask.h23 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
49 #define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14
79 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14
138 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14
164 #define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14
199 #define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14
276 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14
318 #define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14
354 #define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14
395 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_7_0_sh_mask.h238 #define UMCCH0_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
267 #define UMCCH0_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
296 #define UMCCH0_0_PerfMonCtr3_Hi__ThreshCnt__SHIFT 0x14
325 #define UMCCH0_0_PerfMonCtr4_Hi__ThreshCnt__SHIFT 0x14
354 #define UMCCH0_0_PerfMonCtr5_Hi__ThreshCnt__SHIFT 0x14
383 #define UMCCH0_0_PerfMonCtr6_Hi__ThreshCnt__SHIFT 0x14
412 #define UMCCH0_0_PerfMonCtr7_Hi__ThreshCnt__SHIFT 0x14
441 #define UMCCH0_0_PerfMonCtr8_Hi__ThreshCnt__SHIFT 0x14
598 #define UMCCH1_0_PerfMonCtr1_Hi__ThreshCnt__SHIFT 0x14
627 #define UMCCH1_0_PerfMonCtr2_Hi__ThreshCnt__SHIFT 0x14
[all...]
/kernel/linux/linux-5.10/arch/mips/include/asm/
H A Dcacheops.h31 #define Hit_Writeback_Inv 0x14 /* not with Cache_I though */
51 #define Fill_I (Cache_I | 0x14)
78 #define R5K_Page_Invalidate_S (Cache_S | 0x14)
83 #define Page_Invalidate_T (Cache_T | 0x14)
97 #define Cache_Barrier 0x14

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