Searched refs:wptr_offset (Results 1 - 10 of 10) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/ |
| H A D | dmub_srv.h | 263 void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
267 void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_dcn20.c | 271 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn20_set_inbox1_wptr() argument
273 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn20_set_inbox1_wptr()
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| H A D | dmub_dcn20.h | 181 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dmub/ |
| H A D | dmub_srv.h | 354 void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
372 void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_dcn20.c | 295 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn20_set_inbox1_wptr() argument
297 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn20_set_inbox1_wptr()
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| H A D | dmub_dcn31.c | 255 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn31_set_inbox1_wptr() argument
257 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn31_set_inbox1_wptr()
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| H A D | dmub_dcn32.c | 279 void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn32_set_inbox1_wptr() argument
281 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn32_set_inbox1_wptr()
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| H A D | dmub_dcn20.h | 209 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
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| H A D | dmub_dcn31.h | 211 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
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| H A D | dmub_dcn32.h | 214 void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
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