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Searched refs:vmw_read (Results 1 - 13 of 13) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_drv.c540 width = vmw_read(dev_priv, SVGA_REG_WIDTH); in vmw_get_initial_size()
541 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); in vmw_get_initial_size()
698 svga_id = vmw_read(dev_priv, SVGA_REG_ID); in vmw_driver_load()
705 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); in vmw_driver_load()
708 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); in vmw_driver_load()
720 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); in vmw_driver_load()
721 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); in vmw_driver_load()
722 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); in vmw_driver_load()
723 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); in vmw_driver_load()
729 vmw_read(dev_pri in vmw_driver_load()
[all...]
H A Dvmwgfx_fifo.c56 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); in vmw_fifo_have_3d()
122 DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); in vmw_fifo_init()
123 DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); in vmw_fifo_init()
124 DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); in vmw_fifo_init()
126 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_fifo_init()
127 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_fifo_init()
128 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_fifo_init()
136 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); in vmw_fifo_init()
181 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) in vmw_fifo_release()
H A Dvmwgfx_ioctl.c174 (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); in vmw_fill_compat_cap()
230 (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); in vmw_get_cap_3d_ioctl()
H A Dvmwgfx_irq.c114 return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0); in vmw_fifo_idle()
H A Dvmwgfx_kms.c1884 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) { in vmw_kms_write_svga()
1886 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH)); in vmw_kms_write_svga()
2039 num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS); in vmw_du_connector_detect()
H A Dvmwgfx_drv.h688 static inline uint32_t vmw_read(struct vmw_private *dev_priv, in vmw_read() function
/kernel/linux/linux-6.6/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_drv.c442 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
443 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_device_init()
444 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_device_init()
473 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) in vmw_device_fini()
629 width = vmw_read(dev_priv, SVGA_REG_WIDTH); in vmw_get_initial_size()
630 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); in vmw_get_initial_size()
802 svga_id = vmw_read(dev, SVGA_REG_ID); in vmw_detect_version()
892 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); in vmw_driver_load()
897 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); in vmw_driver_load()
923 dev_priv->vram_size = vmw_read(dev_pri in vmw_driver_load()
[all...]
H A Dvmwgfx_devcaps.c96 vmw->devcaps[i] = vmw_read(vmw, SVGA_REG_DEV_CAP); in vmw_devcaps_create()
H A Dvmwgfx_irq.c123 return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0); in vmw_fifo_idle()
H A Dvmwgfx_drv.h706 static inline uint32_t vmw_read(struct vmw_private *dev_priv, in vmw_read() function
1480 fence = vmw_read(dev_priv, SVGA_REG_FENCE); in vmw_fence_read()
1497 status = vmw_read(vmw, SVGA_REG_IRQ_STATUS); in vmw_irq_status_read()
H A Dvmwgfx_kms.c281 mob_max_size = vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); in vmw_du_get_cursor_mob()
282 cursor_max_dim = vmw_read(dev_priv, SVGA_REG_CURSOR_MAX_DIMENSION); in vmw_du_get_cursor_mob()
2139 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) { in vmw_kms_write_svga()
2141 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH)); in vmw_kms_write_svga()
2270 num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS); in vmw_du_connector_detect()
H A Dvmwgfx_cmd.c123 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); in vmw_fifo_create()
H A Dvmwgfx_fence.c88 return vmw_read(vmw, SVGA_REG_FENCE_GOAL); in vmw_fence_goal_read()

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