Searched refs:vlv (Results 1 - 12 of 12) sorted by relevance
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | i9xx_wm.c | 235 dev_priv->display.wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
266 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
1448 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; in vlv_compute_fifo()
1449 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_compute_fifo()
1562 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_set()
1586 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_compute()
1605 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1606 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1607 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1616 &crtc_state->wm.vlv in vlv_raw_plane_wm_is_valid()
[all...] |
| H A D | intel_display_power_map.c | 204 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
211 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
213 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
215 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
217 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
223 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
291 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
294 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
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| H A D | intel_display_power_well.h | 73 } vlv; member
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| H A D | intel_display_core.h | 253 struct vlv_wm_values vlv; member
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| H A D | intel_display_types.h | 953 } vlv; member
1346 /* enable vlv/chv wgc csc? */
1414 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1466 struct vlv_wm_state vlv; member
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| H A D | intel_display_power_well.c | 1066 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_set_power_well()
1115 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_power_well_enabled()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | intel_pm.c | 458 dev_priv->wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
489 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
1705 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; in vlv_compute_fifo()
1706 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_compute_fifo()
1820 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_set()
1845 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_compute()
1864 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1865 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1866 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1875 &crtc_state->wm.vlv in vlv_raw_plane_wm_is_valid()
[all...] |
| H A D | i915_drv.h | 1114 struct vlv_wm_values vlv; member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_display_power.h | 169 } vlv; member
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| H A D | intel_display_types.h | 753 } vlv; member
1088 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1132 struct vlv_wm_state vlv; member
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| H A D | intel_display_power.c | 1280 int pw_idx = power_well->desc->vlv.idx; in vlv_set_power_well()
1329 int pw_idx = power_well->desc->vlv.idx; in vlv_power_well_enabled()
3133 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
3145 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
3157 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
3169 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
3181 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
3190 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
3220 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
3229 .vlv
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/ |
| H A D | intel_clock_gating.c | 633 /* WaDisableBackToBackFlipFix:vlv */ in vlv_init_clock_gating()
638 /* WaDisableDopClockGating:vlv */ in vlv_init_clock_gating()
642 /* This is required by WaCatErrorRejectionIssue:vlv */ in vlv_init_clock_gating()
648 * This implements the WaDisableRCZUnitClockGating:vlv workaround. in vlv_init_clock_gating()
653 /* WaDisableL3Bank2xClockGate:vlv in vlv_init_clock_gating()
659 * WaDisableVLVClockGating_VBIIssue:vlv in vlv_init_clock_gating()
823 CG_FUNCS(vlv); variable
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