| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 292 static void calculate_wm_set_for_vlevel(int vlevel, in calculate_wm_set_for_vlevel() argument
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
419 int vlevel, vlevel_max; in dcn301_calculate_wm_and_dlg_fp() local
431 vlevel = 0; in dcn301_calculate_wm_and_dlg_fp()
433 vlevel = vlevel_max; in dcn301_calculate_wm_and_dlg_fp()
434 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_calculate_wm_and_dlg_fp()
438 vlevel in dcn301_calculate_wm_and_dlg_fp()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.h | 43 int vlevel);
53 int vlevel,
71 int vlevel,
|
| H A D | dcn20_fpu.c | 1138 int vlevel) in dcn20_calculate_dlg_params()
1158 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
1212 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; in dcn20_calculate_dlg_params()
1213 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; in dcn20_calculate_dlg_params()
1219 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; in dcn20_calculate_dlg_params()
1726 int vlevel, in dcn20_calculate_wm()
1738 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn20_calculate_wm()
1742 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn20_calculate_wm()
1751 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; in dcn20_calculate_wm()
1782 pipes[0].clks_cfg.voltage = vlevel; in dcn20_calculate_wm()
1134 dcn20_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn20_calculate_dlg_params() argument
1722 dcn20_calculate_wm(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *out_pipe_cnt, int *pipe_split_from, int vlevel, bool fast_validate) dcn20_calculate_wm() argument
2027 int vlevel = 0; dcn20_validate_bandwidth_internal() local
2135 dcn20_fpu_adjust_dppclk(struct vba_vars_st *v, int vlevel, int max_mpc_comb, int pipe_idx, bool is_validating_bw) dcn20_fpu_adjust_dppclk() argument
2200 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) calculate_wm_set_for_vlevel() argument
2238 int vlevel, vlevel_max; dcn21_calculate_wm() local
2322 int vlevel = 0; dcn21_validate_bandwidth_fp() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 266 int vlevel) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
271 enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
277 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
280 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
283 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
285 vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
287 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
288 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
549 unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; in dcn32_set_phantom_stream_timing() local
550 unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][contex in dcn32_set_phantom_stream_timing()
262 dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
1091 subvp_validate_static_schedulability(struct dc *dc, struct dc_state *context, int vlevel) subvp_validate_static_schedulability() argument
1147 dcn32_full_validate_bw_helper(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *vlevel, int *split, bool *merge, int *pipe_cnt) dcn32_full_validate_bw_helper() argument
1346 dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn32_calculate_dlg_params() argument
1651 int vlevel = context->bw_ctx.dml.soc.num_states; dcn32_internal_validate_bw() local
1959 dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn32_calculate_wm_and_dlg_fpu() argument
[all...] |
| H A D | dcn32_fpu.h | 60 int vlevel);
68 int vlevel);
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.h | 50 int vlevel);
70 int vlevel);
|
| H A D | dcn30_fpu.c | 383 int vlevel) in dcn30_fpu_calculate_wm_and_dlg()
387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
388 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported; in dcn30_fpu_calculate_wm_and_dlg()
406 context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
414 dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true); in dcn30_fpu_calculate_wm_and_dlg()
416 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
417 pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported; in dcn30_fpu_calculate_wm_and_dlg()
424 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
426 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
433 if (vlevel in dcn30_fpu_calculate_wm_and_dlg()
379 dcn30_fpu_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn30_fpu_calculate_wm_and_dlg() argument
691 dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn30_find_dummy_latency_index_for_fw_based_mclk_switch() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.h | 73 int vlevel);
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
|
| H A D | dcn30_resource.c | 1639 int pipe_cnt, i, pipe_idx, vlevel; in dcn30_internal_validate_bw() local
1667 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1668 /* This may adjust vlevel and maxMpcComb */ in dcn30_internal_validate_bw()
1669 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1670 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1673 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1674 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) { in dcn30_internal_validate_bw()
1685 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1686 if (vlevel < contex in dcn30_internal_validate_bw()
2022 dcn30_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn30_calculate_wm_and_dlg() argument
2041 int vlevel = 0; dcn30_validate_bandwidth() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_resource.c | 1026 int vlevel, in calculate_wm_set_for_vlevel()
1035 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1037 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
1038 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1039 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
1095 int vlevel, vlevel_max; in dcn21_calculate_wm() local
1148 vlevel = 0; in dcn21_calculate_wm()
1150 vlevel = vlevel_max; in dcn21_calculate_wm()
1151 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn21_calculate_wm()
1155 vlevel in dcn21_calculate_wm()
1025 calculate_wm_set_for_vlevel( int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) calculate_wm_set_for_vlevel() argument
1179 int vlevel = 0; dcn21_validate_bandwidth_fp() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 1956 int pipe_cnt, i, pipe_idx, vlevel; in dcn30_internal_validate_bw() local
1980 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1981 /* This may adjust vlevel and maxMpcComb */ in dcn30_internal_validate_bw()
1982 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1983 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); in dcn30_internal_validate_bw()
1985 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1986 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { in dcn30_internal_validate_bw()
1997 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1998 if (vlevel < contex in dcn30_internal_validate_bw()
2217 dcn30_calculate_wm_and_dlg_fp( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn30_calculate_wm_and_dlg_fp() argument
2373 dcn30_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn30_calculate_wm_and_dlg() argument
2392 int vlevel = 0; dcn30_validate_bandwidth() local
[all...] |
| H A D | dcn30_resource.h | 62 int vlevel);
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_resource.c | 2652 int vlevel,
2715 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2716 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
2717 v->ModeSupport[vlevel][0])
2720 if (vlevel > context->bw_ctx.dml.soc.num_states)
2721 vlevel = vlevel_split;
2739 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
2741 else if (force_split || v->NoOfDPP[vlevel][max_mpc_com
2649 dcn20_validate_apply_pipe_split_flags( struct dc *dc, struct dc_state *context, int vlevel, int *split, bool *merge) global() argument
2848 int pipe_cnt, i, pipe_idx, vlevel; global() local
2955 dcn20_calculate_wm( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *out_pipe_cnt, int *pipe_split_from, int vlevel) global() argument
3070 dcn20_calculate_dlg_params( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) global() argument
3145 int vlevel = 0; global() local
[all...] |
| H A D | dcn20_resource.h | 124 int vlevel,
160 int vlevel);
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_resource.c | 1833 int vlevel, in dcn20_validate_apply_pipe_split_flags()
1896 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1897 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && in dcn20_validate_apply_pipe_split_flags()
1898 v->ModeSupport[vlevel][0]) in dcn20_validate_apply_pipe_split_flags()
1901 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
1902 vlevel = vlevel_split; in dcn20_validate_apply_pipe_split_flags()
1920 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) in dcn20_validate_apply_pipe_split_flags()
1922 else if (force_split || v->NoOfDPP[vlevel][max_mpc_com in dcn20_validate_apply_pipe_split_flags()
1830 dcn20_validate_apply_pipe_split_flags( struct dc *dc, struct dc_state *context, int vlevel, int *split, bool *merge) dcn20_validate_apply_pipe_split_flags() argument
2029 int pipe_cnt, i, pipe_idx, vlevel; dcn20_fast_validate_bw() local
[all...] |
| H A D | dcn20_resource.h | 127 int vlevel,
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.h | 44 int vlevel);
|
| H A D | dcn31_fpu.c | 484 int vlevel) in dcn31_calculate_wm_and_dlg_fp()
487 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
499 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 in dcn31_calculate_wm_and_dlg_fp()
503 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
505 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
549 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg_fp()
552 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_vactive; in dcn31_calculate_wm_and_dlg_fp()
480 dcn31_calculate_wm_and_dlg_fp( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn31_calculate_wm_and_dlg_fp() argument
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_resource.h | 47 int vlevel);
|
| H A D | dcn31_resource.c | 1724 int vlevel) in dcn31_calculate_wm_and_dlg()
1727 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); in dcn31_calculate_wm_and_dlg()
1760 int vlevel = 0; in dcn31_validate_bandwidth() local
1768 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true); in dcn31_validate_bandwidth()
1785 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); in dcn31_validate_bandwidth()
1720 dcn31_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) dcn31_calculate_wm_and_dlg() argument
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_resource.c | 803 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
828 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
830 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
840 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
841 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
845 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); in dcn21_fast_validate_bw()
904 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); in dcn21_fast_validate_bw()
935 *vlevel_out = vlevel; in dcn21_fast_validate_bw()
|
| /kernel/linux/linux-5.10/arch/arm64/kvm/ |
| H A D | arch_timer.c | 635 bool vlevel, plevel; in kvm_timer_should_notify_user() local
640 vlevel = sregs->device_irq_level & KVM_ARM_DEV_EL1_VTIMER; in kvm_timer_should_notify_user()
643 return kvm_timer_should_fire(vtimer) != vlevel || in kvm_timer_should_notify_user()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_resource_helpers.c | 682 * @vlevel: Voltage level calculated by DML
693 bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel) in dcn32_subvp_vblank_admissable() argument
730 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) in dcn32_subvp_vblank_admissable()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 108 int vlevel);
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 88 int vlevel);
|