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Help
Searched
refs:vgpu_cfg_space
(Results
1 - 8
of
8
) sorted by relevance
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/
H
A
D
cfg_space.c
72
u8 *cfg_base =
vgpu_cfg_space
(vgpu);
in vgpu_pci_cfg_mem_write()
98
pwr = (pci_power_t __force)(*(u16*)(&
vgpu_cfg_space
(vgpu)[off])
in vgpu_pci_cfg_mem_write()
129
memcpy(p_data,
vgpu_cfg_space
(vgpu) + offset, bytes);
in intel_vgpu_emulate_cfg_read()
148
u8 old =
vgpu_cfg_space
(vgpu)[offset];
in emulate_pci_command_write()
170
u32 *pval = (u32 *)(
vgpu_cfg_space
(vgpu) + offset);
in emulate_pci_rom_bar_write()
188
vgpu_cfg_space
(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
in emulate_pci_bar_write()
328
memcpy(
vgpu_cfg_space
(vgpu), gvt->firmware.cfg_space,
in intel_vgpu_init_cfg_space()
332
vgpu_cfg_space
(vgpu)[PCI_CLASS_DEVICE] =
in intel_vgpu_init_cfg_space()
334
vgpu_cfg_space
(vgpu)[PCI_CLASS_PROG] =
in intel_vgpu_init_cfg_space()
339
gmch_ctl = (u16 *)(
vgpu_cfg_space
(vgp
in intel_vgpu_init_cfg_space()
[all...]
H
A
D
interrupt.c
414
control = *(u16 *)(
vgpu_cfg_space
(vgpu) + MSI_CAP_CONTROL(offset));
in inject_virtual_interrupt()
415
addr = *(u32 *)(
vgpu_cfg_space
(vgpu) + MSI_CAP_ADDRESS(offset));
in inject_virtual_interrupt()
416
data = *(u16 *)(
vgpu_cfg_space
(vgpu) + MSI_CAP_DATA(offset));
in inject_virtual_interrupt()
H
A
D
gvt.h
111
#define
vgpu_cfg_space
(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
macro
485
pval = (u32 *)(
vgpu_cfg_space
(vgpu) + offset);
in intel_vgpu_write_pci_bar()
H
A
D
opregion.c
443
if ((
vgpu_cfg_space
(vgpu)[INTEL_GVT_PCI_SWSCI]
in intel_vgpu_emulate_opregion_request()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
H
A
D
cfg_space.c
71
u8 *cfg_base =
vgpu_cfg_space
(vgpu);
in vgpu_pci_cfg_mem_write()
97
pwr = (pci_power_t __force)(*(u16*)(&
vgpu_cfg_space
(vgpu)[off])
in vgpu_pci_cfg_mem_write()
128
memcpy(p_data,
vgpu_cfg_space
(vgpu) + offset, bytes);
in intel_vgpu_emulate_cfg_read()
143
val =
vgpu_cfg_space
(vgpu)[PCI_BASE_ADDRESS_2];
in map_aperture()
145
val = *(u64 *)(
vgpu_cfg_space
(vgpu) + PCI_BASE_ADDRESS_2);
in map_aperture()
147
val = *(u32 *)(
vgpu_cfg_space
(vgpu) + PCI_BASE_ADDRESS_2);
in map_aperture()
171
val =
vgpu_cfg_space
(vgpu)[PCI_BASE_ADDRESS_0];
in trap_gttmmio()
173
start = *(u64 *)(
vgpu_cfg_space
(vgpu) + PCI_BASE_ADDRESS_0);
in trap_gttmmio()
175
start = *(u32 *)(
vgpu_cfg_space
(vgpu) + PCI_BASE_ADDRESS_0);
in trap_gttmmio()
191
u8 old =
vgpu_cfg_space
(vgp
in emulate_pci_command_write()
[all...]
H
A
D
mpt.h
123
control = *(u16 *)(
vgpu_cfg_space
(vgpu) + MSI_CAP_CONTROL(offset));
in intel_gvt_hypervisor_inject_msi()
124
addr = *(u32 *)(
vgpu_cfg_space
(vgpu) + MSI_CAP_ADDRESS(offset));
in intel_gvt_hypervisor_inject_msi()
125
data = *(u16 *)(
vgpu_cfg_space
(vgpu) + MSI_CAP_DATA(offset));
in intel_gvt_hypervisor_inject_msi()
H
A
D
gvt.h
112
#define
vgpu_cfg_space
(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
macro
456
pval = (u32 *)(
vgpu_cfg_space
(vgpu) + offset);
in intel_vgpu_write_pci_bar()
H
A
D
opregion.c
513
if ((
vgpu_cfg_space
(vgpu)[INTEL_GVT_PCI_SWSCI]
in intel_vgpu_emulate_opregion_request()
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