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Searched refs:vdpu_write (Results 1 - 20 of 20) sorted by relevance

/kernel/linux/linux-6.6/drivers/media/platform/verisilicon/
H A Dhantro_g1.c24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
H A Dhantro_g2.c23 vdpu_write(vpu, status, G2_REG_INTERRUPT); in hantro_g2_check_idle()
38 vdpu_write(vpu, 0, G2_REG_INTERRUPT); in hantro_g2_irq()
39 vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); in hantro_g2_irq()
H A Drockchip_vpu_hw.c385 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT); in rockchip_vpu2_vdpu_irq()
386 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL); in rockchip_vpu2_vdpu_irq()
421 vdpu_write(vpu, 0, AV1_REG_INTERRUPT); in rk3588_vpu981_irq()
422 vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG); in rk3588_vpu981_irq()
462 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in rk3066_vpu_dec_reset()
463 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in rk3066_vpu_dec_reset()
479 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT); in rockchip_vpu2_dec_reset()
480 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS); in rockchip_vpu2_dec_reset()
481 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET); in rockchip_vpu2_dec_reset()
H A Dhantro.h407 static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) in vdpu_write() function
417 vdpu_write(vpu, addr & 0xffffffff, offset); in hantro_write_addr()
444 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base); in hantro_reg_write()
H A Dimx8m_vpu_hw.c247 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in imx8m_vpu_g1_irq()
248 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in imx8m_vpu_g1_irq()
H A Drockchip_vpu2_hw_mpeg2_dec.c245 vdpu_write(vpu, reg, VDPU_SWREG(57)); in rockchip_vpu2_mpeg2_dec_run()
H A Dhantro_g1_h264_dec.c281 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_h264_dec_run()
H A Dhantro_g1_mpeg2_dec.c237 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_mpeg2_dec_run()
H A Dhantro_g1_vp8_dec.c508 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_vp8_dec_run()
H A Drockchip_vpu2_hw_h264_dec.c488 vdpu_write(vpu, reg, VDPU_SWREG(57)); in rockchip_vpu2_h264_dec_run()
H A Dhantro_g2_hevc_dec.c624 vdpu_write(vpu, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); in hantro_g2_hevc_dec_run()
H A Dhantro_g2_vp9_dec.c927 vdpu_write(ctx->dev, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); in hantro_g2_vp9_dec_run()
/kernel/linux/linux-5.10/drivers/staging/media/hantro/
H A Drk3288_vpu_hw.c140 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in rk3288_vdpu_irq()
141 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in rk3288_vdpu_irq()
168 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in rk3288_vpu_dec_reset()
169 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in rk3288_vpu_dec_reset()
170 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in rk3288_vpu_dec_reset()
H A Drk3399_vpu_hw.c119 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT); in rk3399_vdpu_irq()
120 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL); in rk3399_vdpu_irq()
147 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT); in rk3399_vpu_dec_reset()
148 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS); in rk3399_vpu_dec_reset()
149 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET); in rk3399_vpu_dec_reset()
H A Dimx8m_vpu_hw.c143 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in imx8m_vpu_g1_irq()
144 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in imx8m_vpu_g1_irq()
H A Dhantro.h357 static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) in vdpu_write() function
394 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base); in hantro_reg_write_s()
H A Dhantro_g1_h264_dec.c303 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_h264_dec_run()
H A Dhantro_g1_mpeg2_dec.c250 vdpu_write(vpu, reg, G1_SWREG(1)); in hantro_g1_mpeg2_dec_run()
H A Drk3399_vpu_hw_mpeg2_dec.c256 vdpu_write(vpu, reg, VDPU_SWREG(57)); in rk3399_vpu_mpeg2_dec_run()
H A Dhantro_g1_vp8_dec.c508 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); in hantro_g1_vp8_dec_run()

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