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Searched refs:udw (Results 1 - 7 of 7) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
H A Dexeclist.c99 status.udw = vgpu_vreg(vgpu, status_reg + 4); in emulate_execlist_status()
118 vgpu_vreg(vgpu, status_reg + 4) = status.udw; in emulate_execlist_status()
120 gvt_dbg_el("vgpu%d: status reg offset %x ldw %x udw %x\n", in emulate_execlist_status()
121 vgpu->id, status_reg, status.ldw, status.udw); in emulate_execlist_status()
153 vgpu_vreg(vgpu, offset + 4) = status->udw; in emulate_csb_update()
171 vgpu->id, write_pointer, offset, status->ldw, status->udw); in emulate_csb_update()
263 status.udw = vgpu_vreg(vgpu, status_reg + 4); in get_next_execlist_slot()
496 desc[0]->udw, desc[0]->ldw, desc[1]->udw, desc[1]->ldw); in intel_vgpu_submit_execlist()
H A Dexeclist.h56 u32 udw; member
79 u32 udw; member
118 u32 udw; member
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/
H A Dexeclist.c99 status.udw = vgpu_vreg(vgpu, status_reg + 4); in emulate_execlist_status()
118 vgpu_vreg(vgpu, status_reg + 4) = status.udw; in emulate_execlist_status()
120 gvt_dbg_el("vgpu%d: status reg offset %x ldw %x udw %x\n", in emulate_execlist_status()
121 vgpu->id, status_reg, status.ldw, status.udw); in emulate_execlist_status()
153 vgpu_vreg(vgpu, offset + 4) = status->udw; in emulate_csb_update()
171 vgpu->id, write_pointer, offset, status->ldw, status->udw); in emulate_csb_update()
263 status.udw = vgpu_vreg(vgpu, status_reg + 4); in get_next_execlist_slot()
496 desc[0]->udw, desc[0]->ldw, desc[1]->udw, desc[1]->ldw); in intel_vgpu_submit_execlist()
H A Dexeclist.h56 u32 udw; member
79 u32 udw; member
118 u32 udw; member
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_color.c849 u32 ldw, u32 udw) in i9xx_lut_10_pack()
852 REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
854 REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
856 REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8; in i9xx_lut_10_pack()
864 u32 ldw, u32 udw) in i9xx_lut_10_pack_slope()
866 int r_exp = REG_FIELD_GET(PALETTE_10BIT_RED_EXP_MASK, udw); in i9xx_lut_10_pack_slope()
867 int r_mant = REG_FIELD_GET(PALETTE_10BIT_RED_MANT_MASK, udw); in i9xx_lut_10_pack_slope()
868 int g_exp = REG_FIELD_GET(PALETTE_10BIT_GREEN_EXP_MASK, udw); in i9xx_lut_10_pack_slope()
869 int g_mant = REG_FIELD_GET(PALETTE_10BIT_GREEN_MANT_MASK, udw); in i9xx_lut_10_pack_slope()
870 int b_exp = REG_FIELD_GET(PALETTE_10BIT_BLUE_EXP_MASK, udw); in i9xx_lut_10_pack_slope()
848 i9xx_lut_10_pack(struct drm_color_lut *color, u32 ldw, u32 udw) i9xx_lut_10_pack() argument
863 i9xx_lut_10_pack_slope(struct drm_color_lut *color, u32 ldw, u32 udw) i9xx_lut_10_pack_slope() argument
896 i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) i965_lut_10p6_pack() argument
942 ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) ilk_lut_12p4_pack() argument
1709 chv_cgm_degamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) chv_cgm_degamma_pack() argument
1743 chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) chv_cgm_gamma_pack() argument
3063 u32 ldw, udw; i9xx_read_lut_10() local
3123 u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1)); i965_read_lut_10p6() local
3173 u32 udw = intel_de_read_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1)); chv_read_cgm_degamma() local
3199 u32 udw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1)); chv_read_cgm_gamma() local
3526 u32 udw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe)); icl_read_lut_multi_segment() local
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H A Dintel_dsb.c102 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) in intel_dsb_emit() argument
115 buf[dsb->free_pos++] = udw; in intel_dsb_emit()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_color.c433 static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) in i965_lut_10p6_pack() argument
435 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | in i965_lut_10p6_pack()
437 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | in i965_lut_10p6_pack()
439 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | in i965_lut_10p6_pack()
463 static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) in icl_lut_multi_seg_pack() argument
465 entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 | in icl_lut_multi_seg_pack()
467 entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) << 6 | in icl_lut_multi_seg_pack()
469 entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6 | in icl_lut_multi_seg_pack()
1029 static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) in chv_cgm_gamma_pack() argument
1033 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 1 in chv_cgm_gamma_pack()
1795 u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1)); i965_read_lut_10p6() local
1838 u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1)); chv_read_cgm_gamma() local
1988 u32 udw = intel_de_read(dev_priv, PREC_PAL_MULTI_SEG_DATA(pipe)); icl_read_lut_multi_segment() local
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