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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgv100.c70 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gv100_grctx_generate_attrib()
120 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gv100_grctx_generate_rop_mapping()
131 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | in gv100_grctx_generate_rop_mapping()
134 u8 v19 = (1 << (j + 0)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
135 u8 v20 = (1 << (j + 1)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
136 u8 v21 = (1 << (j + 2)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
137 u8 v22 = (1 << (j + 3)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
145 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gv100_grctx_generate_rop_mapping()
H A Dgm200.c168 if (gr->gpc_nr == 2 && gr->tpc_total == 8) { in gm200_gr_oneinit_tiles()
169 memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total); in gm200_gr_oneinit_tiles()
172 if (gr->gpc_nr == 4 && gr->tpc_total == 16) { in gm200_gr_oneinit_tiles()
173 memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total); in gm200_gr_oneinit_tiles()
176 if (gr->gpc_nr == 6 && gr->tpc_total == 24) { in gm200_gr_oneinit_tiles()
177 memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total); in gm200_gr_oneinit_tiles()
H A Dgf117.c127 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gf117_gr_init_zcull()
128 const u8 tile_nr = ALIGN(gr->tpc_total, 32); in gf117_gr_init_zcull()
133 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in gf117_gr_init_zcull()
144 gr->tpc_total); in gf117_gr_init_zcull()
H A Dtu102.c55 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in tu102_gr_init_zcull()
56 const u8 tile_nr = ALIGN(gr->tpc_total, 64); in tu102_gr_init_zcull()
61 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in tu102_gr_init_zcull()
72 gr->tpc_total); in tu102_gr_init_zcull()
H A Dctxgf117.c211 ntpcv = gr->tpc_total; in gf117_grctx_generate_rop_mapping()
224 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
230 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
237 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
252 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); in gf117_grctx_generate_attrib()
256 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; in gf117_grctx_generate_attrib()
H A Dctxgp100.c53 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp100_grctx_generate_attrib()
99 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); in gp100_grctx_generate_smid_config()
H A Dctxgm20b.c47 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm20b_grctx_generate_main()
H A Dctxgk20a.c50 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gk20a_grctx_generate_main()
H A Dctxgm200.c49 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); in gm200_grctx_generate_smid_config()
H A Dctxgp102.c49 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp102_grctx_generate_attrib()
H A Dctxgf100.c1071 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); in gf100_grctx_generate_attrib()
1128 ntpcv = gr->tpc_total; in gf100_grctx_generate_rop_mapping()
1141 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gf100_grctx_generate_rop_mapping()
1147 nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) | in gf100_grctx_generate_rop_mapping()
1154 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gf100_grctx_generate_rop_mapping()
1278 u32 atarget = gf100_grctx_alpha_beta_map[gr->tpc_total][i]; in gf100_grctx_generate_alpha_beta_tables()
1283 atarget = max_t(u32, gr->tpc_total * i / 32, 1); in gf100_grctx_generate_alpha_beta_tables()
H A Dgf100.c1106 cfg |= (u32)gr->tpc_total << 8; in gf100_gr_units()
1876 switch (gr->tpc_total) { in gf100_gr_oneinit_tiles()
1889 if (gr->tpc_total % primes[i]) { in gf100_gr_oneinit_tiles()
1929 for (i = 0; i < gr->tpc_total;) { in gf100_gr_oneinit_tiles()
1956 gr->tpc_total += gr->tpc_nr[i]; in gf100_gr_oneinit()
2224 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gf100_gr_init_zcull()
2225 const u8 tile_nr = ALIGN(gr->tpc_total, 32); in gf100_gr_init_zcull()
2230 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in gf100_gr_init_zcull()
2241 gr->tpc_total); in gf100_gr_init_zcull()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgv100.c70 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gv100_grctx_generate_attrib()
123 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gv100_grctx_generate_rop_mapping()
134 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | in gv100_grctx_generate_rop_mapping()
137 u8 v19 = (1 << (j + 0)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
138 u8 v20 = (1 << (j + 1)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
139 u8 v21 = (1 << (j + 2)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
140 u8 v22 = (1 << (j + 3)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
148 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gv100_grctx_generate_rop_mapping()
H A Dgf117.c127 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gf117_gr_init_zcull()
129 const u8 tile_nr = !gr->func->gpc_nr ? ALIGN(gr->tpc_total, 32) : in gf117_gr_init_zcull()
135 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in gf117_gr_init_zcull()
146 gr->tpc_total); in gf117_gr_init_zcull()
H A Dgm200.c167 if (gr->gpc_nr == 2 && gr->tpc_total == 8) { in gm200_gr_oneinit_tiles()
168 memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total); in gm200_gr_oneinit_tiles()
171 if (gr->gpc_nr == 4 && gr->tpc_total == 16) { in gm200_gr_oneinit_tiles()
172 memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total); in gm200_gr_oneinit_tiles()
175 if (gr->gpc_nr == 6 && gr->tpc_total == 24) { in gm200_gr_oneinit_tiles()
176 memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total); in gm200_gr_oneinit_tiles()
H A Dctxgf117.c211 ntpcv = gr->tpc_total; in gf117_grctx_generate_rop_mapping()
224 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
230 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
237 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
253 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; in gf117_grctx_generate_attrib()
H A Dctxgp100.c49 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp100_grctx_generate_attrib()
96 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp100_grctx_generate_attrib_cb_size()
109 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); in gp100_grctx_generate_smid_config()
H A Dgv100.c235 gpc_table = kcalloc(gr->tpc_total, sizeof(*gpc_table), GFP_KERNEL); in gv100_gr_oneinit_sm_id()
236 tpc_table = kcalloc(gr->tpc_total, sizeof(*tpc_table), GFP_KERNEL); in gv100_gr_oneinit_sm_id()
247 for (gtpc = 0; gtpc < gr->tpc_total; gtpc++) { in gv100_gr_oneinit_sm_id()
267 for (gtpc = 0; gtpc < gr->tpc_total; gtpc++) { in gv100_gr_oneinit_sm_id()
H A Dtu102.c56 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in tu102_gr_init_zcull()
62 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in tu102_gr_init_zcull()
73 gr->tpc_total); in tu102_gr_init_zcull()
H A Dctxgp102.c48 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp102_grctx_generate_attrib()
89 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp102_grctx_generate_attrib_cb_size()
H A Dctxgm20b.c49 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm20b_grctx_generate_main()
H A Dctxgk20a.c52 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gk20a_grctx_generate_main()
H A Dctxgm200.c49 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); in gm200_grctx_generate_smid_config()
H A Dctxgf100.c1064 return 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max) * gr->tpc_total; in gf100_grctx_generate_attrib_cb_size()
1106 ntpcv = gr->tpc_total; in gf100_grctx_generate_rop_mapping()
1119 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gf100_grctx_generate_rop_mapping()
1125 nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) | in gf100_grctx_generate_rop_mapping()
1132 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gf100_grctx_generate_rop_mapping()
1256 u32 atarget = gf100_grctx_alpha_beta_map[gr->tpc_total][i]; in gf100_grctx_generate_alpha_beta_tables()
1261 atarget = max_t(u32, gr->tpc_total * i / 32, 1); in gf100_grctx_generate_alpha_beta_tables()
H A Dgf100.c1166 cfg |= (u32)gr->tpc_total << 8; in gf100_gr_units()
1923 switch (gr->tpc_total) { in gf100_gr_oneinit_tiles()
1936 if (gr->tpc_total % primes[i]) { in gf100_gr_oneinit_tiles()
1976 for (i = 0; i < gr->tpc_total;) { in gf100_gr_oneinit_tiles()
2013 gr->tpc_total += gr->tpc_nr[i]; in gf100_gr_oneinit()
2290 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gf100_gr_init_zcull()
2291 const u8 tile_nr = ALIGN(gr->tpc_total, 32); in gf100_gr_init_zcull()
2296 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in gf100_gr_init_zcull()
2307 gr->tpc_total); in gf100_gr_init_zcull()

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