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Searched refs:tiling (Results 1 - 25 of 61) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/tegra/
H A Dfb.c37 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling()
43 tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_TEGRA; in tegra_fb_get_tiling()
45 tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_GPU; in tegra_fb_get_tiling()
52 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; in tegra_fb_get_tiling()
53 tiling->value = 0; in tegra_fb_get_tiling()
57 tiling->mode = TEGRA_BO_TILING_MODE_TILED; in tegra_fb_get_tiling()
58 tiling->value = 0; in tegra_fb_get_tiling()
62 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
63 tiling->value = 0; in tegra_fb_get_tiling()
67 tiling in tegra_fb_get_tiling()
36 tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, struct tegra_bo_tiling *tiling) tegra_fb_get_tiling() argument
[all...]
H A Dhub.c432 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_shared_plane_atomic_check() local
446 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_shared_plane_atomic_check()
450 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_shared_plane_atomic_check()
456 if (tiling->sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU && in tegra_shared_plane_atomic_check()
637 if (tegra_plane_state->tiling.sector_layout == TEGRA_BO_SECTOR_LAYOUT_GPU) in tegra_shared_plane_atomic_update()
717 unsigned long height = tegra_plane_state->tiling.value; in tegra_shared_plane_atomic_update()
720 switch (tegra_plane_state->tiling.mode) { in tegra_shared_plane_atomic_update()
H A Dgem.h49 struct tegra_bo_tiling tiling; member
H A Dplane.h49 struct tegra_bo_tiling tiling; member
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/
H A Di915_gem_tiling.c17 * DOC: buffer object tiling
23 * object, and hence it also doesn't care about tiling or swizzling. There's two
26 * - For X and Y tiling the hardware provides detilers for CPU access, so called
28 * these, and therefore userspace must tell the kernel the object tiling if it
33 * and hence now the tiling. Note that on a subset of platforms with
37 * Since neither of this applies for new tiling layouts on modern platforms like
38 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
47 * @tiling: tiling mod
53 i915_gem_fence_size(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride) i915_gem_fence_size() argument
93 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride) i915_gem_fence_alignment() argument
117 i915_tiling_ok(struct drm_i915_gem_object *obj, unsigned int tiling, unsigned int stride) i915_tiling_ok() argument
220 i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, unsigned int tiling, unsigned int stride) i915_gem_object_set_tiling() argument
[all...]
H A Di915_gem_object.h255 i915_gem_tile_height(unsigned int tiling) in i915_gem_tile_height() argument
257 GEM_BUG_ON(!tiling); in i915_gem_tile_height()
258 return tiling == I915_TILING_Y ? 32 : 8; in i915_gem_tile_height()
275 unsigned int tiling, unsigned int stride);
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/
H A Di915_gem_tiling.c19 * DOC: buffer object tiling
25 * object, and hence it also doesn't care about tiling or swizzling. There's two
28 * - For X and Y tiling the hardware provides detilers for CPU access, so called
30 * these, and therefore userspace must tell the kernel the object tiling if it
35 * and hence now the tiling. Note that on a subset of platforms with
39 * Since neither of this applies for new tiling layouts on modern platforms like
40 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
49 * @tiling: tiling mod
55 i915_gem_fence_size(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride) i915_gem_fence_size() argument
95 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size, unsigned int tiling, unsigned int stride) i915_gem_fence_alignment() argument
119 i915_tiling_ok(struct drm_i915_gem_object *obj, unsigned int tiling, unsigned int stride) i915_tiling_ok() argument
231 i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, unsigned int tiling, unsigned int stride) i915_gem_object_set_tiling() argument
[all...]
H A Di915_gem_tiling.h16 unsigned int tiling, unsigned int stride);
18 unsigned int tiling, unsigned int stride);
H A Di915_gem_object.h334 i915_gem_tile_height(unsigned int tiling) in i915_gem_tile_height() argument
336 GEM_BUG_ON(!tiling); in i915_gem_tile_height()
337 return tiling == I915_TILING_Y ? 32 : 8; in i915_gem_tile_height()
354 unsigned int tiling, unsigned int stride);
/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
H A Dfb.c43 struct tegra_bo_tiling *tiling) in tegra_fb_get_tiling()
49 tiling->mode = TEGRA_BO_TILING_MODE_PITCH; in tegra_fb_get_tiling()
50 tiling->value = 0; in tegra_fb_get_tiling()
54 tiling->mode = TEGRA_BO_TILING_MODE_TILED; in tegra_fb_get_tiling()
55 tiling->value = 0; in tegra_fb_get_tiling()
59 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
60 tiling->value = 0; in tegra_fb_get_tiling()
64 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; in tegra_fb_get_tiling()
65 tiling->value = 1; in tegra_fb_get_tiling()
69 tiling in tegra_fb_get_tiling()
42 tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, struct tegra_bo_tiling *tiling) tegra_fb_get_tiling() argument
[all...]
H A Dhub.c343 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_shared_plane_atomic_check() local
357 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_shared_plane_atomic_check()
361 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_shared_plane_atomic_check()
512 unsigned long height = state->tiling.value; in tegra_shared_plane_atomic_update()
515 switch (state->tiling.mode) { in tegra_shared_plane_atomic_update()
H A Dgem.h43 struct tegra_bo_tiling tiling; member
H A Dplane.h45 struct tegra_bo_tiling tiling; member
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c97 enum client_tiling tiling; member
134 if (buf->tiling == CLIENT_TILING_X && !fastblit_supports_x_tiling(buf->vma->vm->i915)) in fast_blit_ok()
168 if (src->tiling == CLIENT_TILING_4) { in prepare_blit()
171 } else if (src->tiling == CLIENT_TILING_Y) { in prepare_blit()
173 } else if (src->tiling == CLIENT_TILING_X) { in prepare_blit()
180 if (dst->tiling == CLIENT_TILING_4) { in prepare_blit()
183 } else if (dst->tiling == CLIENT_TILING_Y) { in prepare_blit()
185 } else if (dst->tiling == CLIENT_TILING_X) { in prepare_blit()
207 if (src->tiling == CLIENT_TILING_Y) in prepare_blit()
209 if (dst->tiling in prepare_blit()
356 tiled_offset(const struct intel_gt *gt, u64 v, unsigned int stride, enum client_tiling tiling, int x_pos, int y_pos) tiled_offset() argument
412 repr_tiling(enum client_tiling tiling) repr_tiling() argument
[all...]
H A Di915_gem_mman.c35 unsigned int tiling; member
48 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
54 if (tile->tiling == I915_TILING_X) { in tiled_offset()
108 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); in check_partial_mapping()
110 pr_err("Failed to set tiling mode=%u, stride=%u, err=%d\n", in check_partial_mapping()
111 tile->tiling, tile->stride, err); in check_partial_mapping()
115 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); in check_partial_mapping()
161 pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%lu + %u [0x%lx]) of 0x%x, found 0x%x\n", in check_partial_mapping()
166 tile->tiling ? tile_row_pages(obj) : 0, in check_partial_mapping()
167 vma->fence ? vma->fence->id : -1, tile->tiling, til in check_partial_mapping()
321 int tiling; igt_partial_tiling() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_mman.c24 unsigned int tiling; member
37 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
43 if (tile->tiling == I915_TILING_X) { in tiled_offset()
96 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride); in check_partial_mapping()
98 pr_err("Failed to set tiling mode=%u, stride=%u, err=%d\n", in check_partial_mapping()
99 tile->tiling, tile->stride, err); in check_partial_mapping()
103 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); in check_partial_mapping()
149 pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%llu + %u [0x%llx]) of 0x%x, found 0x%x\n", in check_partial_mapping()
154 tile->tiling ? tile_row_pages(obj) : 0, in check_partial_mapping()
155 vma->fence ? vma->fence->id : -1, tile->tiling, til in check_partial_mapping()
304 int tiling; igt_partial_tiling() local
[all...]
H A Di915_gem_client_blt.c139 u32 tiling; member
169 if (src->tiling == I915_TILING_Y) in prepare_blit()
171 if (dst->tiling == I915_TILING_Y) in prepare_blit()
188 if (src->tiling) { in prepare_blit()
194 if (dst->tiling) { in prepare_blit()
287 t->buffers[i].tiling = in tiled_blits_create_buffers()
313 unsigned int tiling) in tiled_offset()
318 if (tiling == I915_TILING_NONE) in tiled_offset()
323 if (tiling == I915_TILING_X) { in tiled_offset()
360 static const char *repr_tiling(int tiling) in repr_tiling() argument
310 tiled_offset(const struct intel_gt *gt, u64 v, unsigned int stride, unsigned int tiling) tiled_offset() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dintel_ggtt_fencing.c43 * have their own tiling state bits and don't need fences.
45 * Also note that fences only support X and Y tiling and hence can't be used for
46 * the fancier new tiling formats like W, Ys and Yf.
89 if (fence->tiling) { in i965_write_fence_reg()
98 if (fence->tiling == I915_TILING_Y) in i965_write_fence_reg()
130 if (fence->tiling) { in i915_write_fence_reg()
132 unsigned int tiling = fence->tiling; in i915_write_fence_reg() local
133 bool is_y_tiled = tiling == I915_TILING_Y; in i915_write_fence_reg()
164 if (fence->tiling) { in i830_write_fence_reg()
[all...]
H A Dintel_ggtt_fencing.h49 * Whether the tiling parameters for the currently
51 * for the purposes of tracking tiling changes we also
59 u32 tiling; member
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dintel_ggtt_fencing.c31 * have their own tiling state bits and don't need fences.
33 * Also note that fences only support X and Y tiling and hence can't be used for
34 * the fancier new tiling formats like W, Ys and Yf.
77 if (fence->tiling) { in i965_write_fence_reg()
86 if (fence->tiling == I915_TILING_Y) in i965_write_fence_reg()
118 if (fence->tiling) { in i915_write_fence_reg()
120 unsigned int tiling = fence->tiling; in i915_write_fence_reg() local
121 bool is_y_tiled = tiling == I915_TILING_Y; in i915_write_fence_reg()
152 if (fence->tiling) { in i830_write_fence_reg()
[all...]
H A Dintel_ggtt_fencing.h30 * Whether the tiling parameters for the currently
32 * for the purposes of tracking tiling changes we also
40 u32 tiling; member
/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
H A Dvc4_render_cl.c440 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup() local
491 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_surface_setup()
492 DRM_DEBUG("Bad tiling format\n"); in vc4_rcl_surface_setup()
525 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_surface_setup()
539 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup() local
568 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_render_config_surface_setup()
569 DRM_DEBUG("Bad tiling format\n"); in vc4_rcl_render_config_surface_setup()
586 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_render_config_surface_setup()
H A Dvc4_plane.c640 u32 tiling, src_y; in vc4_plane_mode_set() local
678 tiling = SCALER_CTL0_TILING_LINEAR; in vc4_plane_mode_set()
741 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
774 tiling = SCALER_CTL0_TILING_64B; in vc4_plane_mode_set()
778 tiling = SCALER_CTL0_TILING_128B; in vc4_plane_mode_set()
782 tiling = SCALER_CTL0_TILING_256B_OR_T; in vc4_plane_mode_set()
816 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx", in vc4_plane_mode_set()
837 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
887 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | in vc4_plane_mode_set()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_plane_initial.c127 switch (plane_config->tiling) { in initial_plane_vma()
134 plane_config->tiling; in initial_plane_vma()
137 MISSING_CASE(plane_config->tiling); in initial_plane_vma()
276 if (plane_config->tiling) in intel_find_initial_plane_obj()
/kernel/linux/linux-6.6/drivers/gpu/drm/vc4/
H A Dvc4_render_cl.c440 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup() local
491 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_surface_setup()
492 DRM_DEBUG("Bad tiling format\n"); in vc4_rcl_surface_setup()
525 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_surface_setup()
539 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup() local
568 if (tiling > VC4_TILING_FORMAT_LT) { in vc4_rcl_render_config_surface_setup()
569 DRM_DEBUG("Bad tiling format\n"); in vc4_rcl_render_config_surface_setup()
586 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_render_config_surface_setup()

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