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Searched refs:sync_cfg_height (Results 1 - 7 of 7) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_pingpong.h23 u32 sync_cfg_height; member
H A Ddpu_encoder_phys_cmd.c375 * By setting sync_cfg_height to near max register value, we essentially in dpu_encoder_phys_cmd_tearcheck_config()
379 tc_cfg.sync_cfg_height = 0xFFF0; in dpu_encoder_phys_cmd_tearcheck_config()
400 phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.sync_cfg_height, in dpu_encoder_phys_cmd_tearcheck_config()
H A Ddpu_hw_pingpong.c110 DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); in dpu_hw_pp_setup_te_config()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_mdss.h468 * @sync_cfg_height: Total vertical lines (display height - 1)
484 u32 sync_cfg_height; member
H A Ddpu_encoder_phys_cmd.c377 * Set the sync_cfg_height to twice vtotal so that if we lose a in dpu_encoder_phys_cmd_tearcheck_config()
381 tc_cfg.sync_cfg_height = mode->vtotal * 2; in dpu_encoder_phys_cmd_tearcheck_config()
400 tc_cfg.sync_cfg_height, tc_cfg.sync_threshold_start, in dpu_encoder_phys_cmd_tearcheck_config()
H A Ddpu_hw_pingpong.c93 DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); in dpu_hw_pp_enable_te()
H A Ddpu_hw_intf.c352 DPU_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); in dpu_hw_intf_enable_te()

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