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Searched refs:subslice_mask (Results 1 - 23 of 23) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c29 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) in intel_sseu_subslice_total()
30 total += hweight8(sseu->subslice_mask[i]); in intel_sseu_subslice_total()
43 mask |= (u32)sseu->subslice_mask[offset + i] << in intel_sseu_get_subslices()
54 memcpy(&sseu->subslice_mask[offset], &ss_mask, sseu->ss_stride); in intel_sseu_set_subslices()
198 u32 subslice_mask, eu_en; in gen10_sseu_info_init() local
229 subslice_mask = (1 << 4) - 1; in gen10_sseu_info_init()
230 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> in gen10_sseu_info_init()
234 u32 subslice_mask_with_eus = subslice_mask; in gen10_sseu_info_init()
273 u8 subslice_mask = 0; in cherryview_sseu_info_init() local
287 subslice_mask | in cherryview_sseu_info_init()
330 u32 fuse2, eu_disable, subslice_mask; gen9_sseu_info_init() local
436 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ bdw_sseu_info_init() local
521 u8 subslice_mask = 0; hsw_sseu_info_init() local
[all...]
H A Dintel_sseu.h28 u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE]; member
53 u8 subslice_mask; member
63 .subslice_mask = sseu->subslice_mask[0], in intel_sseu_from_device_info()
80 mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx]; in intel_sseu_has_subslice()
H A Dintel_sseu_debugfs.c16 memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride); in sseu_copy_subslices()
41 sseu->subslice_mask[0] |= BIT(ss); in cherryview_sseu_device_status()
92 sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask); in gen10_sseu_device_status()
148 sseu->subslice_mask); in gen9_sseu_device_status()
160 sseu->subslice_mask[ss_idx] |= in gen9_sseu_device_status()
189 sseu->subslice_mask); in bdw_sseu_device_status()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c28 return bitmap_weight(sseu->subslice_mask.xehp, in intel_sseu_subslice_total()
29 XEHP_BITMAP_BITS(sseu->subslice_mask)); in intel_sseu_subslice_total()
31 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++) in intel_sseu_subslice_total()
32 total += hweight8(sseu->subslice_mask.hsw[i]); in intel_sseu_subslice_total()
44 return sseu->subslice_mask.hsw[slice]; in intel_sseu_get_hsw_subslices()
157 sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask; in gen11_compute_sseu_info()
174 bitmap_or(sseu->subslice_mask.xehp, in xehp_compute_sseu_info()
177 XEHP_BITMAP_BITS(sseu->subslice_mask)); in xehp_compute_sseu_info()
348 sseu->subslice_mask.hsw[0] |= BIT(0); in cherryview_sseu_info_init()
359 sseu->subslice_mask in cherryview_sseu_info_init()
388 u32 fuse2, eu_disable, subslice_mask; gen9_sseu_info_init() local
494 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ bdw_sseu_info_init() local
579 u8 subslice_mask = 0; hsw_sseu_info_init() local
[all...]
H A Dintel_sseu.h70 intel_sseu_ss_mask_t subslice_mask; member
103 u8 subslice_mask; member
113 .subslice_mask = sseu->subslice_mask.hsw[0], in intel_sseu_from_device_info()
130 return test_bit(subslice, sseu->subslice_mask.xehp); in intel_sseu_has_subslice()
132 return sseu->subslice_mask.hsw[slice] & BIT(subslice); in intel_sseu_has_subslice()
144 return find_next_bit(sseu->subslice_mask.xehp, in intel_sseu_find_first_xehp_dss()
145 XEHP_BITMAP_BITS(sseu->subslice_mask), in intel_sseu_find_first_xehp_dss()
H A Dintel_sseu_debugfs.c37 sseu->subslice_mask.hsw[0] |= BIT(ss); in cherryview_sseu_device_status()
88 sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s]; in gen11_sseu_device_status()
143 sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s]; in gen9_sseu_device_status()
153 sseu->subslice_mask.hsw[s] |= BIT(ss); in gen9_sseu_device_status()
180 sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s]; in bdw_sseu_device_status()
H A Dintel_gt_mcr.c155 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, in intel_gt_mcr_init()
H A Dintel_workarounds.c1136 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); in gen9_wa_init_mcr()
1342 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, in xehp_init_mcr()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c1433 if (!user->slice_mask || !user->subslice_mask || in i915_gem_user_to_context_sseu()
1446 overflows_type(user->subslice_mask, context->subslice_mask) || in i915_gem_user_to_context_sseu()
1457 if (user->subslice_mask & ~device->subslice_mask[0]) in i915_gem_user_to_context_sseu()
1464 context->subslice_mask = user->subslice_mask; in i915_gem_user_to_context_sseu()
1471 unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]); in i915_gem_user_to_context_sseu()
1473 unsigned int req_ss = hweight8(context->subslice_mask); in i915_gem_user_to_context_sseu()
2462 user_sseu.subslice_mask in get_sseu()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c1899 if (!user->slice_mask || !user->subslice_mask || in i915_gem_user_to_context_sseu()
1912 overflows_type(user->subslice_mask, context->subslice_mask) || in i915_gem_user_to_context_sseu()
1923 if (user->subslice_mask & ~dev_subslice_mask) in i915_gem_user_to_context_sseu()
1930 context->subslice_mask = user->subslice_mask; in i915_gem_user_to_context_sseu()
1939 unsigned int req_ss = hweight8(context->subslice_mask); in i915_gem_user_to_context_sseu()
2406 user_sseu.subslice_mask = ce->sseu.subslice_mask; in get_sseu()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_getparam.c152 value = sseu->subslice_mask[0]; in i915_getparam_ioctl()
H A Di915_query.c81 sseu->subslice_mask, subslice_length)) in query_topology_info()
H A Di915_perf.c2783 out_sseu->subslice_mask = in get_default_sseu_config()
2784 ~(~0 << (hweight8(out_sseu->subslice_mask) / 2)); in get_default_sseu_config()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_query.c34 intel_sseu_ss_mask_t subslice_mask) in fill_topology_info()
98 return fill_topology_info(sseu, query_item, sseu->subslice_mask); in query_topology_info()
32 fill_topology_info(const struct sseu_dev_info *sseu, struct drm_i915_query_item *query_item, intel_sseu_ss_mask_t subslice_mask) fill_topology_info() argument
H A Di915_perf.c3233 out_sseu->subslice_mask = in get_default_sseu_config()
3234 ~(~0 << (hweight8(out_sseu->subslice_mask) / 2)); in get_default_sseu_config()
/kernel/linux/linux-5.10/tools/include/uapi/drm/
H A Di915_drm.h1744 __u64 subslice_mask; member
/kernel/linux/linux-5.10/include/uapi/drm/
H A Di915_drm.h1744 __u64 subslice_mask; member
/kernel/linux/linux-6.6/include/uapi/drm/
H A Di915_drm.h2200 __u64 subslice_mask; member
/kernel/linux/patches/linux-6.6/prebuilts/usr/include/drm/
H A Di915_drm.h745 __u64 subslice_mask; member
/kernel/linux/linux-6.6/tools/include/uapi/drm/
H A Di915_drm.h2200 __u64 subslice_mask; member
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/drm/
H A Di915_drm.h745 __u64 subslice_mask; member
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c1267 pg_sseu.subslice_mask = in __igt_ctx_sseu()
1268 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); in __igt_ctx_sseu()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c1283 pg_sseu.subslice_mask = in __igt_ctx_sseu()
1284 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); in __igt_ctx_sseu()

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