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Searched refs:subslice (Results 1 - 13 of 13) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.h39 /* Maximum number of EUs that can exist within a subslice or DSS. */
44 /* The maximum number of bits needed to express each subslice/DSS independently */
81 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
123 int subslice) in intel_sseu_has_subslice()
126 subslice >= sseu->max_subslices) in intel_sseu_has_subslice()
130 return test_bit(subslice, sseu->subslice_mask.xehp); in intel_sseu_has_subslice()
132 return sseu->subslice_mask.hsw[slice] & BIT(subslice); in intel_sseu_has_subslice()
122 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, int subslice) intel_sseu_has_subslice() argument
H A Dintel_workarounds.c545 * Only consider slices where one, and only one, subslice has 7 in skl_tune_iz_hashing()
1119 unsigned int slice, subslice; in gen9_wa_init_mcr() local
1126 * Before any MMIO read into slice/subslice specific registers, MCR in gen9_wa_init_mcr()
1137 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); in gen9_wa_init_mcr()
1138 GEM_BUG_ON(!subslice); in gen9_wa_init_mcr()
1139 subslice--; in gen9_wa_init_mcr()
1145 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); in gen9_wa_init_mcr()
1148 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); in gen9_wa_init_mcr()
1247 unsigned int slice, unsigned int subslice) in __set_mcr_steering()
1245 __set_mcr_steering(struct i915_wa_list *wal, i915_reg_t steering_reg, unsigned int slice, unsigned int subslice) __set_mcr_steering() argument
1265 __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, unsigned int slice, unsigned int subslice) __add_mcr_wa() argument
1280 unsigned int subslice; icl_wa_init_mcr() local
1311 unsigned long slice, subslice = 0, slice_mask = 0; xehp_init_mcr() local
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H A Dintel_sseu.c48 int subslice) in sseu_get_eus()
52 return sseu->eu_mask.xehp[subslice]; in sseu_get_eus()
54 return sseu->eu_mask.hsw[slice][subslice]; in sseu_get_eus()
58 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, in sseu_set_eus() argument
64 sseu->eu_mask.xehp[subslice] = eu_mask; in sseu_set_eus()
66 sseu->eu_mask.hsw[slice][subslice] = eu_mask; in sseu_set_eus()
119 * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
121 * @sseu: SSEU structure containing subslice mask to copy
123 * Copies the subslice mask to a userspace buffer in the format expected by
374 * CHV supports subslice powe in cherryview_sseu_info_init()
47 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, int subslice) sseu_get_eus() argument
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H A Dintel_engine_cs.c1759 int subslice; in intel_engine_get_instdone() local
1780 for_each_ss_steering(iter, engine->gt, slice, subslice) { in intel_engine_get_instdone()
1781 instdone->sampler[slice][subslice] = in intel_engine_get_instdone()
1784 slice, subslice); in intel_engine_get_instdone()
1785 instdone->row[slice][subslice] = in intel_engine_get_instdone()
1788 slice, subslice); in intel_engine_get_instdone()
1792 for_each_ss_steering(iter, engine->gt, slice, subslice) in intel_engine_get_instdone()
1793 instdone->geom_svg[slice][subslice] = in intel_engine_get_instdone()
1796 slice, subslice); in intel_engine_get_instdone()
H A Dintel_gt_regs.h76 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
81 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
507 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.h33 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
73 int subslice) in intel_sseu_has_subslice()
76 int ss_idx = subslice / BITS_PER_BYTE; in intel_sseu_has_subslice()
82 return mask & BIT(subslice % BITS_PER_BYTE); in intel_sseu_has_subslice()
72 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, int subslice) intel_sseu_has_subslice() argument
H A Dintel_sseu.c64 int subslice) in sseu_eu_idx()
68 return slice * slice_stride + subslice * sseu->eu_stride; in sseu_eu_idx()
72 int subslice) in sseu_get_eus()
74 int i, offset = sseu_eu_idx(sseu, slice, subslice); in sseu_get_eus()
84 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, in sseu_set_eus() argument
87 int i, offset = sseu_eu_idx(sseu, slice, subslice); in sseu_set_eus()
109 /* ss_en represents entire subslice mask across all slices */ in gen11_compute_sseu_info()
255 * EU in any one subslice may be fused off for die in gen10_sseu_info_init()
315 * CHV supports subslice power gating on devices with more than in cherryview_sseu_info_init()
316 * one subslice, an in cherryview_sseu_info_init()
63 sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, int subslice) sseu_eu_idx() argument
71 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, int subslice) sseu_get_eus() argument
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H A Dintel_engine_cs.c1059 int slice, int subslice, i915_reg_t reg) in read_subslice_reg()
1068 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); in read_subslice_reg()
1071 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); in read_subslice_reg()
1111 int subslice; in intel_engine_get_instdone() local
1131 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { in intel_engine_get_instdone()
1132 instdone->sampler[slice][subslice] = in intel_engine_get_instdone()
1133 read_subslice_reg(engine, slice, subslice, in intel_engine_get_instdone()
1135 instdone->row[slice][subslice] = in intel_engine_get_instdone()
1136 read_subslice_reg(engine, slice, subslice, in intel_engine_get_instdone()
1058 read_subslice_reg(const struct intel_engine_cs *engine, int slice, int subslice, i915_reg_t reg) read_subslice_reg() argument
H A Dintel_workarounds.c448 * Only consider slices where one, and only one, subslice has 7 in skl_tune_iz_hashing()
1086 unsigned int slice, subslice; in wa_init_mcr() local
1099 * Before any MMIO read into slice/subslice specific registers, MCR in wa_init_mcr()
1109 * to which subslice, or to which L3 bank, the respective mmio reads in wa_init_mcr()
1131 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); in wa_init_mcr()
1132 if (!subslice) { in wa_init_mcr()
1134 "No common index found between subslice mask %x and L3 bank mask %x!\n", in wa_init_mcr()
1136 subslice = fls(l3_en); in wa_init_mcr()
1137 drm_WARN_ON(&i915->drm, !subslice); in wa_init_mcr()
1139 subslice in wa_init_mcr()
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_gpu_error.c442 int subslice; in error_print_instdone() local
457 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) in error_print_instdone()
459 slice, subslice, in error_print_instdone()
460 ee->instdone.sampler[slice][subslice]); in error_print_instdone()
462 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) in error_print_instdone()
464 slice, subslice, in error_print_instdone()
465 ee->instdone.row[slice][subslice]); in error_print_instdone()
471 for_each_ss_steering(iter, ee->engine->gt, slice, subslice) in error_print_instdone()
473 slice, subslice, in error_print_instdone()
474 ee->instdone.geom_svg[slice][subslice]); in error_print_instdone()
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_capture.c300 int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0; in guc_capture_alloc_steered_lists() local
320 for_each_ss_steering(iter, gt, slice, subslice) in guc_capture_alloc_steered_lists()
337 for_each_ss_steering(iter, gt, slice, subslice) { in guc_capture_alloc_steered_lists()
339 __fill_ext_reg(extarray, &gen8_extregs[i], slice, subslice); in guc_capture_alloc_steered_lists()
345 __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice); in guc_capture_alloc_steered_lists()
367 * For certain engine classes, there are slice and subslice in guc_capture_get_device_reglist()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_gpu_error.c434 int subslice; in error_print_instdone() local
448 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) in error_print_instdone()
450 slice, subslice, in error_print_instdone()
451 ee->instdone.sampler[slice][subslice]); in error_print_instdone()
453 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) in error_print_instdone()
455 slice, subslice, in error_print_instdone()
456 ee->instdone.row[slice][subslice]); in error_print_instdone()
H A Di915_reg.h2668 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2672 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
9273 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))

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