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Searched refs:smnPCIE_LC_LINK_WIDTH_CNTL (Results 1 - 11 of 11) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v2_3.c55 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
508 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_lc_spc_mode_wa()
531 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_l1_link_width_reconfig_wa()
533 WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data); in nbio_v2_3_apply_l1_link_width_reconfig_wa()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c73 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
1970 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v11_0_get_current_pcie_link_width_level()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c84 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288 macro
1932 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL), in smu_v13_0_6_get_current_pcie_link_width_level()
H A Dsmu_v13_0.c78 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
2028 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v13_0_get_current_pcie_link_width_level()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
2080 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v11_0_get_current_pcie_link_width_level()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c51 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
2206 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega12_get_current_pcie_link_width_level()
H A Dvega20_hwmgr.c56 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
3316 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_get_current_pcie_link_width_level()
H A Dvega10_hwmgr.c58 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
4607 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega10_get_current_pcie_link_width_level()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c50 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
2228 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega12_get_current_pcie_link_width_level()
H A Dvega20_hwmgr.c55 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
3318 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_get_current_pcie_link_width_level()
H A Dvega10_hwmgr.c57 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 macro
4631 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega10_get_current_pcie_link_width_level()

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