Searched refs:sdma_v5_0_get_reg_offset (Results 1 - 2 of 2) sorted by relevance
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
H A D | sdma_v5_0.c | 167 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) in sdma_v5_0_get_reg_offset() function 316 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr() 318 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_get_wptr() 389 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr() 392 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr() 565 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop() 567 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop() 568 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_stop() 570 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_0_gfx_stop() 625 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(ade in sdma_v5_0_ctx_switch_enable() [all...] |
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
H A D | sdma_v5_0.c | 134 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) in sdma_v5_0_get_reg_offset() function 332 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr() 334 wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_get_wptr() 375 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), in sdma_v5_0_ring_set_wptr() 377 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_0_ring_set_wptr() 534 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop() 536 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop() 537 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_stop() 539 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_0_gfx_stop() 594 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(ade in sdma_v5_0_ctx_switch_enable() [all...] |
Completed in 4 milliseconds