Searched refs:sdm_cfg0 (Results 1 - 2 of 2) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/ |
H A D | dsi_pll_28nm.c | 136 u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; in dsi_pll_28nm_clk_set_rate() local 187 sdm_cfg0 = 0x0; in dsi_pll_28nm_clk_set_rate() 188 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); in dsi_pll_28nm_clk_set_rate() 194 sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP; in dsi_pll_28nm_clk_set_rate() 195 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV( in dsi_pll_28nm_clk_set_rate() 202 DBG("sdm_cfg0=%d", sdm_cfg0); in dsi_pll_28nm_clk_set_rate() 230 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); in dsi_pll_28nm_clk_set_rate()
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/ |
H A D | dsi_phy_28nm.c | 123 u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; in dsi_pll_28nm_clk_set_rate() local 174 sdm_cfg0 = 0x0; in dsi_pll_28nm_clk_set_rate() 175 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); in dsi_pll_28nm_clk_set_rate() 181 sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP; in dsi_pll_28nm_clk_set_rate() 182 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV( in dsi_pll_28nm_clk_set_rate() 189 DBG("sdm_cfg0=%d", sdm_cfg0); in dsi_pll_28nm_clk_set_rate() 219 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); in dsi_pll_28nm_clk_set_rate()
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