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Searched refs:reg_val_offs (Results 1 - 14 of 14) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.c710 uint32_t seq, reg_val_offs = 0, value = 0; in amdgpu_kiq_rreg() local
720 if (amdgpu_device_wb_get(adev, &reg_val_offs)) { in amdgpu_kiq_rreg()
725 amdgpu_ring_emit_rreg(ring, reg, reg_val_offs); in amdgpu_kiq_rreg()
756 value = adev->wb.wb[reg_val_offs]; in amdgpu_kiq_rreg()
757 amdgpu_device_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
765 if (reg_val_offs) in amdgpu_kiq_rreg()
766 amdgpu_device_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
H A Damdgpu_virt.h210 uint32_t reg_val_offs; member
H A Damdgpu_ring.h187 uint32_t reg_val_offs);
H A Dgfx_v9_0.c4089 uint32_t seq, reg_val_offs = 0; in gfx_v9_0_kiq_read_clock() local
4097 if (amdgpu_device_wb_get(adev, &reg_val_offs)) { in gfx_v9_0_kiq_read_clock()
4110 reg_val_offs * 4)); in gfx_v9_0_kiq_read_clock()
4112 reg_val_offs * 4)); in gfx_v9_0_kiq_read_clock()
4143 value = (uint64_t)adev->wb.wb[reg_val_offs] | in gfx_v9_0_kiq_read_clock()
4144 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; in gfx_v9_0_kiq_read_clock()
4145 amdgpu_device_wb_free(adev, reg_val_offs); in gfx_v9_0_kiq_read_clock()
4153 if (reg_val_offs) in gfx_v9_0_kiq_read_clock()
4154 amdgpu_device_wb_free(adev, reg_val_offs); in gfx_v9_0_kiq_read_clock()
5570 uint32_t reg_val_offs) in gfx_v9_0_ring_emit_rreg()
5569 gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) gfx_v9_0_ring_emit_rreg() argument
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H A Dgfx_v8_0.c6386 uint32_t reg_val_offs) in gfx_v8_0_ring_emit_rreg()
6397 reg_val_offs * 4)); in gfx_v8_0_ring_emit_rreg()
6399 reg_val_offs * 4)); in gfx_v8_0_ring_emit_rreg()
6385 gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) gfx_v8_0_ring_emit_rreg() argument
H A Dgfx_v10_0.c8132 uint32_t reg_val_offs) in gfx_v10_0_ring_emit_rreg()
8143 reg_val_offs * 4)); in gfx_v10_0_ring_emit_rreg()
8145 reg_val_offs * 4)); in gfx_v10_0_ring_emit_rreg()
8131 gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) gfx_v10_0_ring_emit_rreg() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.c924 uint32_t seq, reg_val_offs = 0, value = 0; in amdgpu_kiq_rreg() local
937 if (amdgpu_device_wb_get(adev, &reg_val_offs)) { in amdgpu_kiq_rreg()
942 amdgpu_ring_emit_rreg(ring, reg, reg_val_offs); in amdgpu_kiq_rreg()
973 value = adev->wb.wb[reg_val_offs]; in amdgpu_kiq_rreg()
974 amdgpu_device_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
982 if (reg_val_offs) in amdgpu_kiq_rreg()
983 amdgpu_device_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
H A Damdgpu_virt.h237 uint32_t reg_val_offs; member
H A Damdgpu_ring.h219 uint32_t reg_val_offs);
H A Dgfx_v9_0.c3923 uint32_t seq, reg_val_offs = 0; in gfx_v9_0_kiq_read_clock() local
3931 if (amdgpu_device_wb_get(adev, &reg_val_offs)) { in gfx_v9_0_kiq_read_clock()
3944 reg_val_offs * 4)); in gfx_v9_0_kiq_read_clock()
3946 reg_val_offs * 4)); in gfx_v9_0_kiq_read_clock()
3977 value = (uint64_t)adev->wb.wb[reg_val_offs] | in gfx_v9_0_kiq_read_clock()
3978 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; in gfx_v9_0_kiq_read_clock()
3979 amdgpu_device_wb_free(adev, reg_val_offs); in gfx_v9_0_kiq_read_clock()
3987 if (reg_val_offs) in gfx_v9_0_kiq_read_clock()
3988 amdgpu_device_wb_free(adev, reg_val_offs); in gfx_v9_0_kiq_read_clock()
5637 uint32_t reg_val_offs) in gfx_v9_0_ring_emit_rreg()
5636 gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) gfx_v9_0_ring_emit_rreg() argument
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H A Dgfx_v9_4_3.c2651 uint32_t reg_val_offs) in gfx_v9_4_3_ring_emit_rreg()
2662 reg_val_offs * 4)); in gfx_v9_4_3_ring_emit_rreg()
2664 reg_val_offs * 4)); in gfx_v9_4_3_ring_emit_rreg()
2650 gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) gfx_v9_4_3_ring_emit_rreg() argument
H A Dgfx_v8_0.c6358 uint32_t reg_val_offs) in gfx_v8_0_ring_emit_rreg()
6369 reg_val_offs * 4)); in gfx_v8_0_ring_emit_rreg()
6371 reg_val_offs * 4)); in gfx_v8_0_ring_emit_rreg()
6357 gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) gfx_v8_0_ring_emit_rreg() argument
H A Dgfx_v11_0.c5646 uint32_t reg_val_offs) in gfx_v11_0_ring_emit_rreg()
5657 reg_val_offs * 4)); in gfx_v11_0_ring_emit_rreg()
5659 reg_val_offs * 4)); in gfx_v11_0_ring_emit_rreg()
5645 gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) gfx_v11_0_ring_emit_rreg() argument
H A Dgfx_v10_0.c8685 uint32_t reg_val_offs) in gfx_v10_0_ring_emit_rreg()
8696 reg_val_offs * 4)); in gfx_v10_0_ring_emit_rreg()
8698 reg_val_offs * 4)); in gfx_v10_0_ring_emit_rreg()
8684 gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t reg_val_offs) gfx_v10_0_ring_emit_rreg() argument

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