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Searched refs:reg_ofs (Results 1 - 19 of 19) sorted by relevance

/kernel/linux/linux-5.10/drivers/staging/vt6656/
H A Dmac.c82 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_off() argument
89 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_off()
93 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_on() argument
100 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_on()
104 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word) in vnt_mac_write_word() argument
111 return vnt_control_out(priv, MESSAGE_TYPE_WRITE, reg_ofs, in vnt_mac_write_word()
H A Dmac.h364 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits);
365 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits);
366 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word);
/kernel/linux/linux-6.6/drivers/staging/vt6656/
H A Dmac.c80 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_off() argument
87 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_off()
91 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_on() argument
98 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_on()
102 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word) in vnt_mac_write_word() argument
109 return vnt_control_out(priv, MESSAGE_TYPE_WRITE, reg_ofs, in vnt_mac_write_word()
H A Dmac.h362 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits);
363 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits);
364 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word);
/kernel/linux/linux-6.6/drivers/reset/
H A Dreset-ma35d1.c29 u32 reg_ofs; member
135 data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_restart_handler()
149 reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_update()
154 writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_update()
178 reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_status()
/kernel/linux/linux-5.10/arch/arm/mach-bcm/
H A Dplatsmp-brcmstb.c140 const int reg_ofs = cpu_logical_map(cpu) * 8; in cpu_set_boot_addr() local
141 writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs); in cpu_set_boot_addr()
142 writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs); in cpu_set_boot_addr()
/kernel/linux/linux-6.6/arch/arm/mach-bcm/
H A Dplatsmp-brcmstb.c132 const int reg_ofs = cpu_logical_map(cpu) * 8; in cpu_set_boot_addr() local
133 writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs); in cpu_set_boot_addr()
134 writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs); in cpu_set_boot_addr()
/kernel/linux/linux-5.10/drivers/gpu/drm/imx/dcss/
H A Ddcss-ctxld.c341 u32 reg_ofs) in dcss_ctxld_write_irqsafe()
357 ctx[ctx_id][item_idx].ofs = reg_ofs; in dcss_ctxld_write_irqsafe()
362 u32 val, u32 reg_ofs) in dcss_ctxld_write()
365 dcss_ctxld_write_irqsafe(ctxld, ctx_id, val, reg_ofs); in dcss_ctxld_write()
340 dcss_ctxld_write_irqsafe(struct dcss_ctxld *ctxld, u32 ctx_id, u32 val, u32 reg_ofs) dcss_ctxld_write_irqsafe() argument
361 dcss_ctxld_write(struct dcss_ctxld *ctxld, u32 ctx_id, u32 val, u32 reg_ofs) dcss_ctxld_write() argument
H A Ddcss-dev.h117 u32 reg_ofs);
/kernel/linux/linux-6.6/drivers/gpu/drm/imx/dcss/
H A Ddcss-ctxld.c341 u32 reg_ofs) in dcss_ctxld_write_irqsafe()
357 ctx[ctx_id][item_idx].ofs = reg_ofs; in dcss_ctxld_write_irqsafe()
362 u32 val, u32 reg_ofs) in dcss_ctxld_write()
365 dcss_ctxld_write_irqsafe(ctxld, ctx_id, val, reg_ofs); in dcss_ctxld_write()
340 dcss_ctxld_write_irqsafe(struct dcss_ctxld *ctxld, u32 ctx_id, u32 val, u32 reg_ofs) dcss_ctxld_write_irqsafe() argument
361 dcss_ctxld_write(struct dcss_ctxld *ctxld, u32 ctx_id, u32 val, u32 reg_ofs) dcss_ctxld_write() argument
H A Ddcss-dev.h117 u32 reg_ofs);
/kernel/linux/linux-5.10/drivers/gpu/drm/stm/
H A Dltdc.h17 u32 reg_ofs; /* register offset for applicable regs */ member
H A Dltdc.c51 * an extra offset specified with reg_ofs.
55 #define REG_OFS (ldev->caps.reg_ofs)
1163 ldev->caps.reg_ofs = REG_OFS_NONE; in ltdc_get_caps()
1179 ldev->caps.reg_ofs = REG_OFS_4; in ltdc_get_caps()
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-cdce925.c227 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_prepare() local
233 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_prepare()
262 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); in cdce925_pll_prepare()
265 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); in cdce925_pll_prepare()
274 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_unprepare() local
277 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_unprepare()
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-cdce925.c227 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_prepare() local
233 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_prepare()
262 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); in cdce925_pll_prepare()
265 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); in cdce925_pll_prepare()
274 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_unprepare() local
277 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_unprepare()
/kernel/linux/linux-6.6/include/drm/bridge/
H A Dsamsung-dsim.h52 const unsigned int *reg_ofs; member
/kernel/linux/linux-5.10/drivers/gpu/drm/exynos/
H A Dexynos_drm_dsi.c243 const unsigned int *reg_ofs; member
325 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in exynos_dsi_write()
330 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in exynos_dsi_read()
454 .reg_ofs = exynos_reg_ofs,
466 .reg_ofs = exynos_reg_ofs,
478 .reg_ofs = exynos_reg_ofs,
488 .reg_ofs = exynos5433_reg_ofs,
499 .reg_ofs = exynos5433_reg_ofs,
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
H A Dsamsung-dsim.c403 .reg_ofs = exynos_reg_ofs,
420 .reg_ofs = exynos_reg_ofs,
437 .reg_ofs = exynos_reg_ofs,
451 .reg_ofs = exynos5433_reg_ofs,
466 .reg_ofs = exynos5433_reg_ofs,
481 .reg_ofs = exynos5433_reg_ofs,
523 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_write()
528 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_read()
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-mt8173.c920 u32 reg_ofs; member
927 .reg_ofs = _reg_ofs, \
1016 base + cku->reg_ofs); in mtk_apmixedsys_init()

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