reg_ctrl2 (reference) in projects: kernel - OpenGrok search results

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Searched refs:reg_ctrl2 (Results 1 - 3 of 3) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/can/
H A D	flexcan.c	1223 u32 reg_fdcbt, reg_ctrl2; in flexcan_set_bittiming_cbt() local 1259 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_set_bittiming_cbt() 1260 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN; in flexcan_set_bittiming_cbt() 1262 reg_ctrl2 \|= FLEXCAN_CTRL2_ISOCANFDEN; in flexcan_set_bittiming_cbt() 1264 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2); in flexcan_set_bittiming_cbt() 1265 priv->write(reg_ctrl2, &regs->ctrl2); in flexcan_set_bittiming_cbt() 1328 u32 reg_ctrl2; in flexcan_ram_init() local 1338 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_ram_init() 1339 reg_ctrl2 \|= FLEXCAN_CTRL2_WRMFRZ; in flexcan_ram_init() 1340 priv->write(reg_ctrl2, in flexcan_ram_init() 1364 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr; flexcan_chip_start() local [all...]
/kernel/linux/linux-6.6/drivers/net/can/flexcan/
H A D	flexcan-core.c	1222 u32 reg_fdcbt, reg_ctrl2; in flexcan_set_bittiming_cbt() local 1258 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_set_bittiming_cbt() 1259 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN; in flexcan_set_bittiming_cbt() 1261 reg_ctrl2 \|= FLEXCAN_CTRL2_ISOCANFDEN; in flexcan_set_bittiming_cbt() 1263 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2); in flexcan_set_bittiming_cbt() 1264 priv->write(reg_ctrl2, &regs->ctrl2); in flexcan_set_bittiming_cbt() 1327 u32 reg_ctrl2; in flexcan_ram_init() local 1337 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_ram_init() 1338 reg_ctrl2 \|= FLEXCAN_CTRL2_WRMFRZ; in flexcan_ram_init() 1339 priv->write(reg_ctrl2, in flexcan_ram_init() 1429 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr; flexcan_chip_start() local [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/
H A D	dsi_host.c	831 u32 reg, reg_ctrl, reg_ctrl2; in dsi_update_dsc_timing() local 868 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); in dsi_update_dsc_timing() 873 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; in dsi_update_dsc_timing() 874 reg_ctrl2 \|= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); in dsi_update_dsc_timing() 877 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); in dsi_update_dsc_timing()

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