regChainOffset (reference) in projects: kernel - OpenGrok search results

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Searched refs:regChainOffset (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
H A D	eeprom_def.c	419 u8 txRxAttenLocal, int regChainOffset, int i) in ath9k_hw_def_set_gain() 426 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 429 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 432 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 435 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 439 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 442 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 450 AR_PHY_RXGAIN + regChainOffset, in ath9k_hw_def_set_gain() 453 AR_PHY_RXGAIN + regChainOffset, in ath9k_hw_def_set_gain() 456 REG_RMW(ah, AR_PHY_RXGAIN + regChainOffset, in ath9k_hw_def_set_gain() 416 ath9k_hw_def_set_gain(struct ath_hw ah, struct modal_eep_header pModal, struct ar5416_eeprom_def *eep, u8 txRxAttenLocal, int regChainOffset, int i) ath9k_hw_def_set_gain() argument 471 int i, regChainOffset; ath9k_hw_def_set_board_values() local 778 u32 reg32, regOffset, regChainOffset; ath9k_hw_set_def_power_cal_table() local [all...]
H A D	eeprom_9287.c	365 u32 reg32, regOffset, regChainOffset, regval; in ath9k_hw_set_ar9287_power_cal_table() local 410 regChainOffset = i * 0x1000; in ath9k_hw_set_ar9287_power_cal_table() 455 AR_PHY_TPCRG5 + regChainOffset, in ath9k_hw_set_ar9287_power_cal_table() 477 (672 << 2) + regChainOffset; in ath9k_hw_set_ar9287_power_cal_table() 855 u32 regChainOffset, regval; in ath9k_hw_ar9287_set_board_values() local 864 regChainOffset = i * 0x1000; in ath9k_hw_ar9287_set_board_values() 866 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, in ath9k_hw_ar9287_set_board_values() 869 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_ar9287_set_board_values() 870 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) in ath9k_hw_ar9287_set_board_values() 880 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_ar9287_set_board_values() [all...]
H A D	eeprom_4k.c	`296 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local 333 regChainOffset = i * 0x1000; in ath9k_hw_set_4k_power_cal_table() 346 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, in ath9k_hw_set_4k_power_cal_table() 358 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; in ath9k_hw_set_4k_power_cal_table() 365 i, regChainOffset, regOffset, in ath9k_hw_set_4k_power_cal_table()`
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/
H A D	eeprom_def.c	419 u8 txRxAttenLocal, int regChainOffset, int i) in ath9k_hw_def_set_gain() 426 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 429 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 432 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 435 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 439 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 442 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain() 450 AR_PHY_RXGAIN + regChainOffset, in ath9k_hw_def_set_gain() 453 AR_PHY_RXGAIN + regChainOffset, in ath9k_hw_def_set_gain() 456 REG_RMW(ah, AR_PHY_RXGAIN + regChainOffset, in ath9k_hw_def_set_gain() 416 ath9k_hw_def_set_gain(struct ath_hw ah, struct modal_eep_header pModal, struct ar5416_eeprom_def *eep, u8 txRxAttenLocal, int regChainOffset, int i) ath9k_hw_def_set_gain() argument 471 int i, regChainOffset; ath9k_hw_def_set_board_values() local 778 u32 reg32, regOffset, regChainOffset; ath9k_hw_set_def_power_cal_table() local [all...]
H A D	eeprom_9287.c	365 u32 reg32, regOffset, regChainOffset, regval; in ath9k_hw_set_ar9287_power_cal_table() local 410 regChainOffset = i * 0x1000; in ath9k_hw_set_ar9287_power_cal_table() 455 AR_PHY_TPCRG5 + regChainOffset, in ath9k_hw_set_ar9287_power_cal_table() 477 (672 << 2) + regChainOffset; in ath9k_hw_set_ar9287_power_cal_table() 854 u32 regChainOffset, regval; in ath9k_hw_ar9287_set_board_values() local 863 regChainOffset = i * 0x1000; in ath9k_hw_ar9287_set_board_values() 865 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, in ath9k_hw_ar9287_set_board_values() 868 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_ar9287_set_board_values() 869 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) in ath9k_hw_ar9287_set_board_values() 879 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_ar9287_set_board_values() [all...]
H A D	eeprom_4k.c	`296 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local 333 regChainOffset = i * 0x1000; in ath9k_hw_set_4k_power_cal_table() 346 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, in ath9k_hw_set_4k_power_cal_table() 358 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; in ath9k_hw_set_4k_power_cal_table() 365 i, regChainOffset, regOffset, in ath9k_hw_set_4k_power_cal_table()`

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