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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Ddmag84.c67 nvkm_kmap(chan->ramfc); in g84_fifo_dma_new()
68 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); in g84_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in g84_fifo_dma_new()
70 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); in g84_fifo_dma_new()
71 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); in g84_fifo_dma_new()
72 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); in g84_fifo_dma_new()
73 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in g84_fifo_dma_new()
74 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in g84_fifo_dma_new()
75 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); in g84_fifo_dma_new()
76 nvkm_wo32(chan->ramfc, in g84_fifo_dma_new()
[all...]
H A Ddmanv50.c67 nvkm_kmap(chan->ramfc); in nv50_fifo_dma_new()
68 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
70 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
71 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); in nv50_fifo_dma_new()
72 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); in nv50_fifo_dma_new()
73 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in nv50_fifo_dma_new()
74 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in nv50_fifo_dma_new()
75 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); in nv50_fifo_dma_new()
76 nvkm_wo32(chan->ramfc, in nv50_fifo_dma_new()
[all...]
H A Dgpfifog84.c71 nvkm_kmap(chan->ramfc); in g84_fifo_gpfifo_new()
72 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in g84_fifo_gpfifo_new()
73 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in g84_fifo_gpfifo_new()
74 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in g84_fifo_gpfifo_new()
75 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); in g84_fifo_gpfifo_new()
76 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); in g84_fifo_gpfifo_new()
77 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in g84_fifo_gpfifo_new()
78 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in g84_fifo_gpfifo_new()
79 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); in g84_fifo_gpfifo_new()
80 nvkm_wo32(chan->ramfc, in g84_fifo_gpfifo_new()
[all...]
H A Ddmanv40.c79 nvkm_kmap(imem->ramfc); in nv40_fifo_dma_engine_fini()
80 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000); in nv40_fifo_dma_engine_fini()
81 nvkm_done(imem->ramfc); in nv40_fifo_dma_engine_fini()
110 nvkm_kmap(imem->ramfc); in nv40_fifo_dma_engine_init()
111 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst); in nv40_fifo_dma_engine_init()
112 nvkm_done(imem->ramfc); in nv40_fifo_dma_engine_init()
222 chan->ramfc = chan->base.chid * 128; in nv40_fifo_dma_new()
224 nvkm_kmap(imem->ramfc); in nv40_fifo_dma_new()
[all...]
H A Ddmanv04.c79 struct nvkm_memory *fctx = device->imem->ramfc; in nv04_fifo_dma_fini()
83 u32 data = chan->ramfc; in nv04_fifo_dma_fini()
97 c = fifo->ramfc; in nv04_fifo_dma_fini()
108 c = fifo->ramfc; in nv04_fifo_dma_fini()
145 const struct nv04_fifo_ramfc *c = fifo->ramfc; in nv04_fifo_dma_dtor()
147 nvkm_kmap(imem->ramfc); in nv04_fifo_dma_dtor()
149 nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000); in nv04_fifo_dma_dtor()
151 nvkm_done(imem->ramfc); in nv04_fifo_dma_dtor()
203 chan->ramfc in nv04_fifo_dma_new()
[all...]
H A Ddmanv17.c75 chan->ramfc = chan->base.chid * 64; in nv17_fifo_dma_new()
77 nvkm_kmap(imem->ramfc); in nv17_fifo_dma_new()
78 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv17_fifo_dma_new()
79 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv17_fifo_dma_new()
80 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); in nv17_fifo_dma_new()
81 nvkm_wo32(imem->ramfc, chan->ramfc in nv17_fifo_dma_new()
[all...]
H A Ddmanv10.c74 chan->ramfc = chan->base.chid * 32; in nv10_fifo_dma_new()
76 nvkm_kmap(imem->ramfc); in nv10_fifo_dma_new()
77 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); in nv10_fifo_dma_new()
78 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); in nv10_fifo_dma_new()
79 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); in nv10_fifo_dma_new()
80 nvkm_wo32(imem->ramfc, chan->ramfc in nv10_fifo_dma_new()
[all...]
H A Dgpfifonv50.c71 nvkm_kmap(chan->ramfc); in nv50_fifo_gpfifo_new()
72 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in nv50_fifo_gpfifo_new()
73 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in nv50_fifo_gpfifo_new()
74 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); in nv50_fifo_gpfifo_new()
75 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); in nv50_fifo_gpfifo_new()
76 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); in nv50_fifo_gpfifo_new()
77 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in nv50_fifo_gpfifo_new()
78 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in nv50_fifo_gpfifo_new()
79 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); in nv50_fifo_gpfifo_new()
80 nvkm_wo32(chan->ramfc, in nv50_fifo_gpfifo_new()
[all...]
H A Dnv17.c58 struct nvkm_memory *ramfc = imem->ramfc; in nv17_fifo_init() local
67 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | in nv17_fifo_init()
H A Dnv40.c68 struct nvkm_memory *ramfc = imem->ramfc; in nv40_fifo_init() local
96 nvkm_memory_addr(ramfc)) >> 16) | in nv40_fifo_init()
H A Dnv04.c306 struct nvkm_memory *ramfc = imem->ramfc; in nv04_fifo_init() local
315 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); in nv04_fifo_init()
329 int index, int nr, const struct nv04_fifo_ramfc *ramfc, in nv04_fifo_new_()
337 fifo->ramfc = ramfc; in nv04_fifo_new_()
328 nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, int index, int nr, const struct nv04_fifo_ramfc *ramfc, struct nvkm_fifo **pfifo) nv04_fifo_new_() argument
H A Dnv04.h17 const struct nv04_fifo_ramfc *ramfc; member
H A Dchannv04.h11 u32 ramfc; member
H A Dchannv50.c198 u64 addr = chan->ramfc->addr >> 12; in nv50_fifo_chan_init()
213 nvkm_gpuobj_del(&chan->ramfc); in nv50_fifo_chan_dtor()
253 &chan->ramfc); in nv50_fifo_chan_ctor()
H A Dchannv50.h12 struct nvkm_gpuobj *ramfc; member
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dnv40.c41 struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc; in nv40_chan_ramfc_write() local
46 nvkm_kmap(ramfc); in nv40_chan_ramfc_write()
47 nvkm_wo32(ramfc, base + 0x00, offset); in nv40_chan_ramfc_write()
48 nvkm_wo32(ramfc, base + 0x04, offset); in nv40_chan_ramfc_write()
49 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4); in nv40_chan_ramfc_write()
50 nvkm_wo32(ramfc, base + 0x18, 0x30000000 | in nv40_chan_ramfc_write()
57 nvkm_wo32(ramfc, base + 0x3c, 0x0001ffff); in nv40_chan_ramfc_write()
58 nvkm_done(ramfc); in nv40_chan_ramfc_write()
105 .ramfc
129 struct nvkm_memory *ramfc = device->imem->ramfc; nv40_ectx_bind() local
188 struct nvkm_memory *ramfc = imem->ramfc; nv40_fifo_init() local
[all...]
H A Dnv17.c40 struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc; in nv17_chan_ramfc_write() local
45 nvkm_kmap(ramfc); in nv17_chan_ramfc_write()
46 nvkm_wo32(ramfc, base + 0x00, offset); in nv17_chan_ramfc_write()
47 nvkm_wo32(ramfc, base + 0x04, offset); in nv17_chan_ramfc_write()
48 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4); in nv17_chan_ramfc_write()
49 nvkm_wo32(ramfc, base + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | in nv17_chan_ramfc_write()
55 nvkm_done(ramfc); in nv17_chan_ramfc_write()
87 .ramfc = &nv17_chan_ramfc,
99 struct nvkm_memory *ramfc in nv17_fifo_init() local
[all...]
H A Dnv10.c39 struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc; in nv10_chan_ramfc_write() local
44 nvkm_kmap(ramfc); in nv10_chan_ramfc_write()
45 nvkm_wo32(ramfc, base + 0x00, offset); in nv10_chan_ramfc_write()
46 nvkm_wo32(ramfc, base + 0x04, offset); in nv10_chan_ramfc_write()
47 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4); in nv10_chan_ramfc_write()
48 nvkm_wo32(ramfc, base + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | in nv10_chan_ramfc_write()
54 nvkm_done(ramfc); in nv10_chan_ramfc_write()
81 .ramfc = &nv10_chan_ramfc,
H A Dg84.c39 nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 8); in g84_chan_bind()
61 ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->inst, &chan->ramfc); in g84_chan_ramfc_write()
69 nvkm_kmap(chan->ramfc); in g84_chan_ramfc_write()
70 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in g84_chan_ramfc_write()
71 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in g84_chan_ramfc_write()
72 nvkm_wo32(chan->ramfc, 0x48, chan->push->node->offset >> 4); in g84_chan_ramfc_write()
73 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(offset)); in g84_chan_ramfc_write()
74 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(offset) | (limit2 << 16)); in g84_chan_ramfc_write()
75 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in g84_chan_ramfc_write()
76 nvkm_wo32(chan->ramfc, in g84_chan_ramfc_write()
[all...]
H A Dnv04.c45 struct nvkm_memory *fctx = device->imem->ramfc; in nv04_chan_stop()
62 c = chan->func->ramfc->layout; in nv04_chan_stop()
73 c = chan->func->ramfc->layout; in nv04_chan_stop()
105 struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc; in nv04_chan_ramfc_clear() local
106 const struct nvkm_ramfc_layout *c = chan->func->ramfc->layout; in nv04_chan_ramfc_clear()
108 nvkm_kmap(ramfc); in nv04_chan_ramfc_clear()
110 nvkm_wo32(ramfc, chan->ramfc_offset + c->ctxp, 0x00000000); in nv04_chan_ramfc_clear()
112 nvkm_done(ramfc); in nv04_chan_ramfc_clear()
118 struct nvkm_memory *ramfc in nv04_chan_ramfc_write() local
472 struct nvkm_memory *ramfc = imem->ramfc; nv04_fifo_init() local
[all...]
H A Dnv50.c76 nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 12); in nv50_chan_bind()
86 ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, chan->inst, &chan->ramfc); in nv50_chan_ramfc_write()
102 nvkm_kmap(chan->ramfc); in nv50_chan_ramfc_write()
103 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in nv50_chan_ramfc_write()
104 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in nv50_chan_ramfc_write()
105 nvkm_wo32(chan->ramfc, 0x48, chan->push->node->offset >> 4); in nv50_chan_ramfc_write()
106 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(offset)); in nv50_chan_ramfc_write()
107 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(offset) | (limit2 << 16)); in nv50_chan_ramfc_write()
108 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in nv50_chan_ramfc_write()
109 nvkm_wo32(chan->ramfc, in nv50_chan_ramfc_write()
[all...]
H A Dchan.c269 if (chan->func->ramfc->clear) in nvkm_chan_del()
270 chan->func->ramfc->clear(chan); in nvkm_chan_del()
276 nvkm_gpuobj_del(&chan->ramfc); in nvkm_chan_del()
360 (!func->ramfc->ctxdma != !dmaobj) || in nvkm_chan_new_()
361 ((func->ramfc->devm < devm) && devm != BIT(0)) || in nvkm_chan_new_()
362 (!func->ramfc->priv && priv)) { in nvkm_chan_new_()
366 func->userd->bar < 0, userd, func->ramfc->ctxdma, dmaobj, in nvkm_chan_new_()
367 func->ramfc->devm, devm, func->ramfc->priv, priv); in nvkm_chan_new_()
432 if (func->ramfc in nvkm_chan_new_()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dinstmem.h19 struct nvkm_memory *ramfc; member
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dinstmem.h24 struct nvkm_memory *ramfc; member
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A Dnv04.c185 &imem->base.ramfc); in nv04_instmem_oneinit()
202 nvkm_memory_unref(&imem->base.ramfc); in nv04_instmem_dtor()

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