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Searched refs:r_clk (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7722.c30 static struct clk r_clk = { variable
42 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
61 .parent = &r_clk,
88 &r_clk,
145 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
146 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
153 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
156 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
171 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7366.c27 static struct clk r_clk = { variable
39 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
58 .parent = &r_clk,
85 &r_clk,
154 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
155 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
185 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7724.c34 static struct clk r_clk = { variable
46 /* The fll multiplies the 32khz r_clk, may be used instead of extal */
67 .parent = &r_clk,
116 &r_clk,
216 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
217 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
229 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0),
230 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0),
261 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7723.c31 static struct clk r_clk = { variable
43 /* The dll multiplies the 32khz r_clk, may be used instead of extal */
62 .parent = &r_clk,
89 &r_clk,
155 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
156 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
171 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
181 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
196 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7343.c27 static struct clk r_clk = { variable
39 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
58 .parent = &r_clk,
82 &r_clk,
151 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
152 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
171 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
187 CLKDEV_CON_ID("rclk", &r_clk),
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7722.c30 static struct clk r_clk = { variable
42 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
61 .parent = &r_clk,
88 &r_clk,
145 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
146 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
153 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
156 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
171 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7366.c27 static struct clk r_clk = { variable
39 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
58 .parent = &r_clk,
85 &r_clk,
154 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
155 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
185 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7724.c34 static struct clk r_clk = { variable
46 /* The fll multiplies the 32khz r_clk, may be used instead of extal */
67 .parent = &r_clk,
116 &r_clk,
216 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
217 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
229 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0),
230 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0),
261 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7723.c31 static struct clk r_clk = { variable
43 /* The dll multiplies the 32khz r_clk, may be used instead of extal */
62 .parent = &r_clk,
89 &r_clk,
155 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
156 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
171 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
181 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
196 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7343.c27 static struct clk r_clk = { variable
39 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
58 .parent = &r_clk,
82 &r_clk,
151 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
152 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
171 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
187 CLKDEV_CON_ID("rclk", &r_clk),
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7269.c26 static struct clk r_clk = { variable
84 &r_clk,
135 [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
140 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7264.c29 static struct clk r_clk = { variable
58 &r_clk,
101 [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
106 CLKDEV_CON_ID("rclk", &r_clk),
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7269.c26 static struct clk r_clk = { variable
84 &r_clk,
135 [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
140 CLKDEV_CON_ID("rclk", &r_clk),
H A Dclock-sh7264.c29 static struct clk r_clk = { variable
58 &r_clk,
101 [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
106 CLKDEV_CON_ID("rclk", &r_clk),
/kernel/linux/linux-5.10/drivers/iio/adc/
H A Dad9467.c351 long r_clk; in ad9467_write_raw() local
357 r_clk = clk_round_rate(st->clk, val); in ad9467_write_raw()
358 if (r_clk < 0 || r_clk > info->max_rate) { in ad9467_write_raw()
360 "Error setting ADC sample rate %ld", r_clk); in ad9467_write_raw()
364 return clk_set_rate(st->clk, r_clk); in ad9467_write_raw()
/kernel/linux/linux-6.6/drivers/iio/adc/
H A Dad9467.c356 long r_clk; in ad9467_write_raw() local
362 r_clk = clk_round_rate(st->clk, val); in ad9467_write_raw()
363 if (r_clk < 0 || r_clk > info->max_rate) { in ad9467_write_raw()
365 "Error setting ADC sample rate %ld", r_clk); in ad9467_write_raw()
369 return clk_set_rate(st->clk, r_clk); in ad9467_write_raw()

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