Home
last modified time | relevance | path

Searched refs:pwr_width (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/bcm/
H A Dclk-iproc.h122 unsigned int pwr_width; member
H A Dclk-iproc-pll.c198 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_disable()
209 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_disable()
221 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_enable()
228 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_enable()
H A Dclk-nsp.c26 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
H A Dclk-cygnus.c28 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
H A Dclk-ns2.c26 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
H A Dclk-sr.c16 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
/kernel/linux/linux-6.6/drivers/clk/bcm/
H A Dclk-iproc.h112 unsigned int pwr_width; member
H A Dclk-iproc-pll.c188 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_disable()
199 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_disable()
211 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); in __pll_enable()
218 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; in __pll_enable()
H A Dclk-nsp.c16 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
H A Dclk-cygnus.c18 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
H A Dclk-ns2.c16 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
H A Dclk-sr.c16 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \

Completed in 7 milliseconds