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Searched refs:prediv (Results 1 - 25 of 54) sorted by relevance

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/kernel/linux/linux-6.6/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
84 unsigned prediv : 6; member
97 unsigned int prediv; member
120 .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
152 u32 prediv; member
164 .prediv = 8,
170 .prediv = 6,
176 .prediv = 24,
182 .prediv = 4,
188 .prediv
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/kernel/linux/linux-5.10/drivers/clk/mmp/
H A Dclk-audio.c118 unsigned int prediv; in audio_pll_recalc_rate() local
135 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { in audio_pll_recalc_rate()
136 if (predivs[prediv].parent_rate != parent_rate) in audio_pll_recalc_rate()
145 val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract); in audio_pll_recalc_rate()
146 val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk); in audio_pll_recalc_rate()
147 val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk); in audio_pll_recalc_rate()
156 freq = predivs[prediv].freq_vco; in audio_pll_recalc_rate()
168 unsigned int prediv; in audio_pll_round_rate() local
196 unsigned int prediv; audio_pll_set_rate() local
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/kernel/linux/linux-6.6/drivers/clk/mmp/
H A Dclk-audio.c120 unsigned int prediv; in audio_pll_recalc_rate() local
137 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { in audio_pll_recalc_rate()
138 if (predivs[prediv].parent_rate != parent_rate) in audio_pll_recalc_rate()
147 val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract); in audio_pll_recalc_rate()
148 val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk); in audio_pll_recalc_rate()
149 val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk); in audio_pll_recalc_rate()
158 freq = predivs[prediv].freq_vco; in audio_pll_recalc_rate()
170 unsigned int prediv; in audio_pll_round_rate() local
198 unsigned int prediv; audio_pll_set_rate() local
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/kernel/linux/linux-5.10/arch/mips/ar7/
H A Dclock.c71 u32 prediv; member
98 static void approximate(int base, int target, int *prediv, in approximate() argument
109 *prediv = j; in approximate()
115 static void calculate(int base, int target, int *prediv, int *postdiv, in calculate() argument
120 for (*prediv = 1; *prediv <= 32; (*prediv)++) { in calculate()
121 tmp_base = base / *prediv; in calculate()
131 if (base / *prediv * *mul / *postdiv != target) { in calculate()
132 approximate(base, target, prediv, postdi in calculate()
166 int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1; tnetd7300_get_clock() local
208 int prediv, postdiv, mul; tnetd7300_set_clock() local
261 tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, int prediv, int postdiv, int postdiv2, int mul, u32 frequency) tnetd7200_set_clock() argument
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/kernel/linux/linux-6.6/arch/mips/ar7/
H A Dclock.c73 u32 prediv; member
100 static void approximate(int base, int target, int *prediv, in approximate() argument
111 *prediv = j; in approximate()
117 static void calculate(int base, int target, int *prediv, int *postdiv, in calculate() argument
122 for (*prediv = 1; *prediv <= 32; (*prediv)++) { in calculate()
123 tmp_base = base / *prediv; in calculate()
133 if (base / *prediv * *mul / *postdiv != target) { in calculate()
134 approximate(base, target, prediv, postdi in calculate()
168 int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1; tnetd7300_get_clock() local
210 int prediv, postdiv, mul; tnetd7300_set_clock() local
271 tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, int prediv, int postdiv, int postdiv2, int mul, u32 frequency) tnetd7200_set_clock() argument
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/kernel/linux/linux-5.10/arch/c6x/platforms/
H A Dpll.c267 u32 ctrl, mult = 0, prediv = 0, postdiv = 0; in clk_pllclk_recalc() local
288 prediv = pll_read(pll, PLLPRE); in clk_pllclk_recalc()
289 if (prediv & PLLDIV_EN) in clk_pllclk_recalc()
290 prediv = (prediv & PLLDIV_RATIO_MASK) + 1; in clk_pllclk_recalc()
292 prediv = 0; in clk_pllclk_recalc()
303 if (prediv) in clk_pllclk_recalc()
304 rate /= prediv; in clk_pllclk_recalc()
313 prediv, mult, postdiv, rate / 1000000); in clk_pllclk_recalc()
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
H A Dtua6100.c62 u32 prediv; in tua6100_set_params() local
105 prediv = (c->frequency * _R_VAL) / (_ri / 1000); in tua6100_set_params()
106 div = prediv / _P_VAL; in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
H A Dtua6100.c62 u32 prediv; in tua6100_set_params() local
105 prediv = (c->frequency * _R_VAL) / (_ri / 1000); in tua6100_set_params()
106 div = prediv / _P_VAL; in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
H A Dccu_mux.c19 u16 prediv = 1; in ccu_mux_get_prediv() local
28 return common->prediv; in ccu_mux_get_prediv()
41 prediv = cm->fixed_predivs[i].div; in ccu_mux_get_prediv()
53 prediv = div + 1; in ccu_mux_get_prediv()
57 return prediv; in ccu_mux_get_prediv()
H A Dccu_gate.c82 rate /= cg->common.prediv; in ccu_gate_recalc_rate()
94 div = cg->common.prediv; in ccu_gate_round_rate()
/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
H A Dccu_mux.c21 u16 prediv = 1; in ccu_mux_get_prediv() local
30 return common->prediv; in ccu_mux_get_prediv()
43 prediv = cm->fixed_predivs[i].div; in ccu_mux_get_prediv()
55 prediv = div + 1; in ccu_mux_get_prediv()
59 return prediv; in ccu_mux_get_prediv()
H A Dccu_gate.c85 rate /= cg->common.prediv; in ccu_gate_recalc_rate()
97 div = cg->common.prediv; in ccu_gate_round_rate()
H A Dccu_gate.h77 .prediv = _prediv, \
105 .prediv = _prediv, \
/kernel/linux/linux-5.10/drivers/clk/pistachio/
H A Dclk-pll.c273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
276 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_frac_recalc_rate()
293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
417 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_laint_recalc_rate()
425 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2); in pll_gf40lp_laint_recalc_rate()
/kernel/linux/linux-6.6/drivers/clk/pistachio/
H A Dclk-pll.c273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
276 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_frac_recalc_rate()
293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
417 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_laint_recalc_rate()
425 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2); in pll_gf40lp_laint_recalc_rate()
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
H A Dda850.c359 unsigned int prediv; member
368 .prediv = 1,
377 .prediv = 1,
386 .prediv = 2,
395 .prediv = 1,
404 .prediv = 1,
413 .prediv = 1,
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-composite-8m.c52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers()
58 *prediv = 1; in imx8m_clk_composite_compute_dividers()
66 *prediv = div1; in imx8m_clk_composite_compute_dividers()
50 imx8m_clk_composite_compute_dividers(unsigned long rate, unsigned long parent_rate, int *prediv, int *postdiv) imx8m_clk_composite_compute_dividers() argument
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-vt8500.c351 u32 *multiplier, u32 *prediv) in vt8500_find_pll_bits()
359 *prediv = 1; in vt8500_find_pll_bits()
363 /* use the prediv to double the resolution */ in vt8500_find_pll_bits()
364 *prediv = 2; in vt8500_find_pll_bits()
366 *prediv = 1; in vt8500_find_pll_bits()
368 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
369 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
350 vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, u32 *multiplier, u32 *prediv) vt8500_find_pll_bits() argument
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-vt8500.c351 u32 *multiplier, u32 *prediv) in vt8500_find_pll_bits()
359 *prediv = 1; in vt8500_find_pll_bits()
363 /* use the prediv to double the resolution */ in vt8500_find_pll_bits()
364 *prediv = 2; in vt8500_find_pll_bits()
366 *prediv = 1; in vt8500_find_pll_bits()
368 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
369 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
350 vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, u32 *multiplier, u32 *prediv) vt8500_find_pll_bits() argument
H A Dclk-versaclock3.c245 unsigned int prediv, premul; in vc3_pfd_recalc_rate() local
249 regmap_read(vc3->regmap, pfd->offs, &prediv); in vc3_pfd_recalc_rate()
252 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
259 mdiv = VC3_PLL1_M_DIV(prediv); in vc3_pfd_recalc_rate()
262 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
270 mdiv = VC3_PLL2_M_DIV(prediv); in vc3_pfd_recalc_rate()
273 if (prediv & pfd->mdiv1_bitmsk) in vc3_pfd_recalc_rate()
276 mdiv = VC3_PLL3_M_DIV(prediv); in vc3_pfd_recalc_rate()
279 if (prediv & pfd->mdiv2_bitmsk) in vc3_pfd_recalc_rate()
/kernel/linux/linux-5.10/drivers/clk/keystone/
H A Dpll.c81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
96 prediv = (val & pll_data->plld_mask); in clk_pllclk_recalc()
109 rate /= (prediv + 1); in clk_pllclk_recalc()
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-composite-8m.c52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers()
58 *prediv = 1; in imx8m_clk_composite_compute_dividers()
66 *prediv = div1; in imx8m_clk_composite_compute_dividers()
50 imx8m_clk_composite_compute_dividers(unsigned long rate, unsigned long parent_rate, int *prediv, int *postdiv) imx8m_clk_composite_compute_dividers() argument
/kernel/linux/linux-6.6/drivers/clk/keystone/
H A Dpll.c81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
96 prediv = (val & pll_data->plld_mask); in clk_pllclk_recalc()
109 rate /= (prediv + 1); in clk_pllclk_recalc()
/kernel/linux/linux-5.10/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c185 u8 prediv; member
241 /* 5Mhz < Fref / prediv < 40MHz */ in inno_dsidphy_pll_calc_rate()
281 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
324 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_dsidphy_mipi_mode_enable()
449 u8 prediv = 2; in inno_dsidphy_lvds_mode_enable() local
462 REG_PREDIV_MASK, REG_PREDIV(prediv)); in inno_dsidphy_lvds_mode_enable()
/kernel/linux/linux-6.6/drivers/media/i2c/
H A Dtc358746.c876 dev_dbg(dev, "Found PLL settings: freq:%lu prediv:%u multi:%u postdiv:%u\n", in tc358746_find_pll_settings()
1093 const unsigned char prediv[] = { 2, 4, 8 }; in tc358746_find_mclk_settings() local
1132 /* First check the prediv */ in tc358746_find_mclk_settings()
1133 for (i = 0; i < ARRAY_SIZE(prediv); i++) { in tc358746_find_mclk_settings()
1134 postdiv = mclkdiv / prediv[i]; in tc358746_find_mclk_settings()
1140 mclk_prediv = prediv[i]; in tc358746_find_mclk_settings()
1142 best_mclk_rate = pll_rate / (prediv[i] * postdiv); in tc358746_find_mclk_settings()
1147 /* No suitable prediv found, so try to adjust the postdiv */ in tc358746_find_mclk_settings()
1174 dev_dbg(dev, "Found MCLK settings: freq:%lu prediv:%u postdiv:%u\n", in tc358746_find_mclk_settings()
1184 unsigned int prediv, postdi in tc358746_recalc_rate() local
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