| /kernel/linux/linux-5.10/arch/mips/ath79/ |
| H A D | clock.c | 238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
315 cpu_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
317 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
325 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
327 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
335 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
337 ahb_rate = cpu_pll / (postdiv in ar934x_clocks_init()
356 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; qca953x_clocks_init() local
439 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; qca955x_clocks_init() local
522 u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; qca956x_clocks_init() local
[all...] |
| /kernel/linux/linux-6.6/arch/mips/ath79/ |
| H A D | clock.c | 238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
315 cpu_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
317 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
325 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
327 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
335 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
337 ahb_rate = cpu_pll / (postdiv in ar934x_clocks_init()
356 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; qca953x_clocks_init() local
439 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; qca955x_clocks_init() local
522 u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; qca956x_clocks_init() local
[all...] |
| /kernel/linux/linux-5.10/arch/mips/ar7/ |
| H A D | clock.c | 72 u32 postdiv; member
99 int *postdiv, int *mul) in approximate()
110 *postdiv = k; in approximate()
115 static void calculate(int base, int target, int *prediv, int *postdiv, in calculate() argument
124 *postdiv = tmp_base / tmp_gcd; in calculate()
127 if ((*postdiv > 0) & (*postdiv <= 32)) in calculate()
131 if (base / *prediv * *mul / *postdiv != target) { in calculate()
132 approximate(base, target, prediv, postdiv, mul); in calculate()
133 tmp_freq = base / *prediv * *mul / *postdiv; in calculate()
98 approximate(int base, int target, int *prediv, int *postdiv, int *mul) approximate() argument
167 int postdiv = (ctrl & POSTDIV_MASK) + 1; tnetd7300_get_clock() local
208 int prediv, postdiv, mul; tnetd7300_set_clock() local
261 tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, int prediv, int postdiv, int postdiv2, int mul, u32 frequency) tnetd7200_set_clock() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 63 u32 pcw, int postdiv) in __mtk_pll_recalc_rate()
86 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
116 int postdiv) in mtk_pll_set_rate_regs()
123 /* set postdiv */ in mtk_pll_set_rate_regs()
126 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; in mtk_pll_set_rate_regs()
128 /* postdiv and pcw need to set at the same time if on same register */ in mtk_pll_set_rate_regs()
154 * @postdiv: The post divider (output)
159 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
179 *postdiv in mtk_pll_calc_values()
62 __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, u32 pcw, int postdiv) __mtk_pll_recalc_rate() argument
115 mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, int postdiv) mtk_pll_set_rate_regs() argument
201 u32 postdiv; mtk_pll_set_rate() local
213 u32 postdiv; mtk_pll_recalc_rate() local
230 int postdiv; mtk_pll_round_rate() local
[all...] |
| /kernel/linux/linux-6.6/arch/mips/ar7/ |
| H A D | clock.c | 74 u32 postdiv; member
101 int *postdiv, int *mul) in approximate()
112 *postdiv = k; in approximate()
117 static void calculate(int base, int target, int *prediv, int *postdiv, in calculate() argument
126 *postdiv = tmp_base / tmp_gcd; in calculate()
129 if ((*postdiv > 0) & (*postdiv <= 32)) in calculate()
133 if (base / *prediv * *mul / *postdiv != target) { in calculate()
134 approximate(base, target, prediv, postdiv, mul); in calculate()
135 tmp_freq = base / *prediv * *mul / *postdiv; in calculate()
100 approximate(int base, int target, int *prediv, int *postdiv, int *mul) approximate() argument
169 int postdiv = (ctrl & POSTDIV_MASK) + 1; tnetd7300_get_clock() local
210 int prediv, postdiv, mul; tnetd7300_set_clock() local
271 tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, int prediv, int postdiv, int postdiv2, int mul, u32 frequency) tnetd7200_set_clock() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 41 u32 pcw, int postdiv) in __mtk_pll_recalc_rate()
64 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
94 int postdiv) in mtk_pll_set_rate_regs()
101 /* set postdiv */ in mtk_pll_set_rate_regs()
104 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; in mtk_pll_set_rate_regs()
106 /* postdiv and pcw need to set at the same time if on same register */ in mtk_pll_set_rate_regs()
132 * @postdiv: The post divider (output)
137 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
157 *postdiv in mtk_pll_calc_values()
40 __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, u32 pcw, int postdiv) __mtk_pll_recalc_rate() argument
93 mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, int postdiv) mtk_pll_set_rate_regs() argument
179 u32 postdiv; mtk_pll_set_rate() local
190 u32 postdiv; mtk_pll_recalc_rate() local
207 int postdiv; mtk_pll_round_rate() local
[all...] |
| H A D | clk-fhctl.c | 171 static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv) in __set_postdiv() argument
177 regval |= (ffs(postdiv) - 1) << pll->data->pd_shift; in __set_postdiv()
182 unsigned int postdiv) in fhctl_hopping()
193 if (postdiv) { in fhctl_hopping()
196 if (postdiv > pll_postdiv) in fhctl_hopping()
197 __set_postdiv(pll, postdiv); in fhctl_hopping()
206 if (postdiv && postdiv < pll_postdiv) in fhctl_hopping()
207 __set_postdiv(pll, postdiv); in fhctl_hopping()
181 fhctl_hopping(struct mtk_fh *fh, unsigned int new_dds, unsigned int postdiv) fhctl_hopping() argument
|
| H A D | clk-pllfh.c | 33 u32 postdiv; in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
|
| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| H A D | clk-audio.c | 119 unsigned int postdiv; in audio_pll_recalc_rate() local
138 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_recalc_rate()
144 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_recalc_rate()
152 val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern); in audio_pll_recalc_rate()
157 freq /= postdivs[postdiv].divisor; in audio_pll_recalc_rate()
169 unsigned int postdiv; in audio_pll_round_rate() local
175 for (postdiv = 0; postdiv < ARRAY_SIZ in audio_pll_round_rate()
197 unsigned int postdiv; audio_pll_set_rate() local
[all...] |
| H A D | clk-pll.c | 49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
71 postdiv = (val >> pll->postdiv_shift) & 0x7; in mmp_clk_pll_recalc_rate()
76 do_div(rate, postdivs[postdiv]); in mmp_clk_pll_recalc_rate()
|
| /kernel/linux/linux-6.6/drivers/clk/mmp/ |
| H A D | clk-audio.c | 121 unsigned int postdiv; in audio_pll_recalc_rate() local
140 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_recalc_rate()
146 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_recalc_rate()
154 val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern); in audio_pll_recalc_rate()
159 freq /= postdivs[postdiv].divisor; in audio_pll_recalc_rate()
171 unsigned int postdiv; in audio_pll_round_rate() local
177 for (postdiv = 0; postdiv < ARRAY_SIZ in audio_pll_round_rate()
199 unsigned int postdiv; audio_pll_set_rate() local
[all...] |
| H A D | clk-pll.c | 49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
71 postdiv = (val >> pll->postdiv_shift) & 0x7; in mmp_clk_pll_recalc_rate()
76 do_div(rate, postdivs[postdiv]); in mmp_clk_pll_recalc_rate()
|
| /kernel/linux/linux-5.10/drivers/clk/keystone/ |
| H A D | pll.c | 45 * @postdiv: Fixed post divider
60 u32 postdiv; member
81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
100 postdiv = ((val & pll_data->clkod_mask) >> in clk_pllclk_recalc()
103 postdiv = readl(pll_data->pllod); in clk_pllclk_recalc()
104 postdiv = ((postdiv & pll_data->clkod_mask) >> in clk_pllclk_recalc()
107 postdiv = pll_data->postdiv; in clk_pllclk_recalc()
111 rate /= postdiv; in clk_pllclk_recalc()
[all...] |
| /kernel/linux/linux-6.6/drivers/clk/keystone/ |
| H A D | pll.c | 45 * @postdiv: Fixed post divider
60 u32 postdiv; member
81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
100 postdiv = ((val & pll_data->clkod_mask) >> in clk_pllclk_recalc()
103 postdiv = readl(pll_data->pllod); in clk_pllclk_recalc()
104 postdiv = ((postdiv & pll_data->clkod_mask) >> in clk_pllclk_recalc()
107 postdiv = pll_data->postdiv; in clk_pllclk_recalc()
111 rate /= postdiv; in clk_pllclk_recalc()
[all...] |
| /kernel/linux/linux-5.10/arch/c6x/platforms/ |
| H A D | pll.c | 267 u32 ctrl, mult = 0, prediv = 0, postdiv = 0; in clk_pllclk_recalc() local
295 postdiv = pll_read(pll, PLLPOST); in clk_pllclk_recalc()
296 if (postdiv & PLLDIV_EN) in clk_pllclk_recalc()
297 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1; in clk_pllclk_recalc()
299 postdiv = 1; in clk_pllclk_recalc()
307 if (postdiv) in clk_pllclk_recalc()
308 rate /= postdiv; in clk_pllclk_recalc()
313 prediv, mult, postdiv, rate / 1000000); in clk_pllclk_recalc()
|
| /kernel/linux/linux-6.6/drivers/clk/microchip/ |
| H A D | clk-mpfs.c | 102 u32 mult, ref_div, postdiv; in mpfs_clk_msspll_recalc_rate() local
108 postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; in mpfs_clk_msspll_recalc_rate()
109 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()
111 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); in mpfs_clk_msspll_recalc_rate()
139 u32 mult, ref_div, postdiv; in mpfs_clk_msspll_set_rate() local
157 postdiv = readl_relaxed(postdiv_addr); in mpfs_clk_msspll_set_rate()
158 postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); in mpfs_clk_msspll_set_rate()
159 writel_relaxed(postdiv, postdiv_addr); in mpfs_clk_msspll_set_rate()
|
| /kernel/linux/linux-6.6/drivers/media/i2c/ |
| H A D | tc358746.c | 818 u8 postdiv; in tc358746_find_pll_settings() local
826 postdiv = 1; in tc358746_find_pll_settings()
828 postdiv = 2; in tc358746_find_pll_settings()
830 postdiv = 4; in tc358746_find_pll_settings()
832 postdiv = 8; in tc358746_find_pll_settings()
842 tmp = fout * p * postdiv; in tc358746_find_pll_settings()
849 do_div(tmp, p * postdiv); in tc358746_find_pll_settings()
868 tc358746->pll_post_div = postdiv; in tc358746_find_pll_settings()
876 dev_dbg(dev, "Found PLL settings: freq:%lu prediv:%u multi:%u postdiv:%u\n", in tc358746_find_pll_settings()
877 best_freq, p_best, m_best, postdiv); in tc358746_find_pll_settings()
1096 unsigned int postdiv, mclkdiv; tc358746_find_mclk_settings() local
1184 unsigned int prediv, postdiv; tc358746_recalc_rate() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/ |
| H A D | dsi_pll_14nm.c | 680 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_recalc_rate() local
681 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_recalc_rate()
683 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_recalc_rate()
684 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_recalc_rate()
693 postdiv->flags, width); in dsi_pll_14nm_postdiv_recalc_rate()
700 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_round_rate() local
701 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_round_rate()
706 postdiv->width, in dsi_pll_14nm_postdiv_round_rate()
707 postdiv->flags); in dsi_pll_14nm_postdiv_round_rate()
713 struct dsi_pll_14nm_postdiv *postdiv in dsi_pll_14nm_postdiv_set_rate() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_14nm.c | 605 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_recalc_rate() local
606 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_recalc_rate()
608 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_recalc_rate()
609 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_recalc_rate()
618 postdiv->flags, width); in dsi_pll_14nm_postdiv_recalc_rate()
625 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_round_rate() local
626 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_round_rate()
631 postdiv->width, in dsi_pll_14nm_postdiv_round_rate()
632 postdiv->flags); in dsi_pll_14nm_postdiv_round_rate()
638 struct dsi_pll_14nm_postdiv *postdiv in dsi_pll_14nm_postdiv_set_rate() local
[all...] |
| /kernel/linux/linux-5.10/arch/arm/mach-davinci/ |
| H A D | da850.c | 361 unsigned int postdiv; member
370 .postdiv = 1,
379 .postdiv = 1,
388 .postdiv = 1,
397 .postdiv = 2,
406 .postdiv = 3,
415 .postdiv = 5,
|
| /kernel/linux/linux-6.6/drivers/clk/visconti/ |
| H A D | pll.c | 59 u32 postdiv, val; in visconti_pll_get_params() local
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG); in visconti_pll_get_params()
71 rate_table->postdiv1 = postdiv & PLL_POSTDIV_MASK; in visconti_pll_get_params()
72 rate_table->postdiv2 = (postdiv >> 4) & PLL_POSTDIV_MASK; in visconti_pll_get_params()
|
| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| H A D | clk-composite-8m.c | 52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers()
59 *postdiv = 1; in imx8m_clk_composite_compute_dividers()
67 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
50 imx8m_clk_composite_compute_dividers(unsigned long rate, unsigned long parent_rate, int *prediv, int *postdiv) imx8m_clk_composite_compute_dividers() argument
|
| /kernel/linux/linux-6.6/drivers/clk/ |
| H A D | clk-tps68470.c | 35 unsigned int postdiv; member
46 * hclk_# = osc_in * (((plldiv*2)+320) / (xtaldiv+30)) * (1 / 2^postdiv)
59 * osc_in xtaldiv plldiv postdiv hclk_#
171 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
172 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv); in tps68470_clk_set_rate()
|
| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| H A D | clk-composite-8m.c | 52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers()
59 *postdiv = 1; in imx8m_clk_composite_compute_dividers()
67 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
50 imx8m_clk_composite_compute_dividers(unsigned long rate, unsigned long parent_rate, int *prediv, int *postdiv) imx8m_clk_composite_compute_dividers() argument
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/ |
| H A D | lontium-lt9611.c | 193 static void lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int postdiv) in lt9611_pcr_setup() argument
195 unsigned int pcr_m = mode->clock * 5 * postdiv / 27000; in lt9611_pcr_setup()
245 static int lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int *postdiv) in lt9611_pll_setup() argument
266 *postdiv = 1; in lt9611_pll_setup()
269 *postdiv = 2; in lt9611_pll_setup()
272 *postdiv = 4; in lt9611_pll_setup()
916 unsigned int postdiv; in lt9611_bridge_mode_set() local
922 lt9611_pll_setup(lt9611, mode, &postdiv); in lt9611_bridge_mode_set()
924 lt9611_pcr_setup(lt9611, mode, postdiv); in lt9611_bridge_mode_set()
|