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Searched refs:pll_state (Results 1 - 11 of 11) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c1766 struct intel_cx0pll_state *pll_state = &crtc_state->cx0pll_state; in intel_c10pll_update_pll() local
1773 pll_state->ssc_enabled = in intel_c10pll_update_pll()
1778 if (pll_state->ssc_enabled) in intel_c10pll_update_pll()
1781 drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); in intel_c10pll_update_pll()
1783 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
1809 struct intel_c10pll_state *pll_state) in intel_c10pll_readout_hw_state()
1826 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
1827 pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane, in intel_c10pll_readout_hw_state()
1830 pll_state->cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
1831 pll_state in intel_c10pll_readout_hw_state()
1808 intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c10pll_state *pll_state) intel_c10pll_readout_hw_state() argument
1840 const struct intel_c10pll_state *pll_state = &crtc_state->cx0pll_state.c10; intel_c10_pll_program() local
1905 intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state) intel_c20_compute_hdmi_tmds_pll() argument
2061 intel_c20pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c20pll_state *pll_state) intel_c20pll_readout_hw_state() argument
2240 const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20; intel_c20_pll_program() local
2336 intel_c10pll_calc_port_clock(struct intel_encoder *encoder, const struct intel_c10pll_state *pll_state) intel_c10pll_calc_port_clock() argument
2363 intel_c20pll_calc_port_clock(struct intel_encoder *encoder, const struct intel_c20pll_state *pll_state) intel_c20pll_calc_port_clock() argument
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H A Dintel_dpll_mgr.c92 const struct intel_dpll_hw_state *pll_state);
310 const struct intel_dpll_hw_state *pll_state, in intel_find_shared_dpll()
332 if (memcmp(pll_state, in intel_find_shared_dpll()
334 sizeof(*pll_state)) == 0) { in intel_find_shared_dpll()
383 const struct intel_dpll_hw_state *pll_state) in intel_reference_shared_dpll()
391 shared_dpll[id].hw_state = *pll_state; in intel_reference_shared_dpll()
923 const struct intel_dpll_hw_state *pll_state) in hsw_ddi_wrpll_get_freq()
927 u32 wrpll = pll_state->wrpll; in hsw_ddi_wrpll_get_freq()
1047 const struct intel_dpll_hw_state *pll_state) in hsw_ddi_lcpll_get_freq()
1098 const struct intel_dpll_hw_state *pll_state) in hsw_ddi_spll_get_freq()
308 intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_dpll_hw_state *pll_state, unsigned long dpll_mask) intel_find_shared_dpll() argument
380 intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) intel_reference_shared_dpll() argument
921 hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) hsw_ddi_wrpll_get_freq() argument
1045 hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) hsw_ddi_lcpll_get_freq() argument
1096 hsw_ddi_spll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) hsw_ddi_spll_get_freq() argument
1630 skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) skl_ddi_wrpll_get_freq() argument
1778 skl_ddi_lcpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) skl_ddi_lcpll_get_freq() argument
1856 skl_ddi_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) skl_ddi_pll_get_freq() argument
2236 bxt_ddi_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) bxt_ddi_pll_get_freq() argument
2615 icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) icl_ddi_tbt_pll_get_freq() argument
2686 icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) icl_ddi_combo_pll_get_freq() argument
2747 icl_calc_dpll_state(struct drm_i915_private *i915, const struct skl_wrpll_params *pll_params, struct intel_dpll_hw_state *pll_state) icl_calc_dpll_state() argument
2853 icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, struct intel_dpll_hw_state *pll_state) icl_calc_mg_pll_state() argument
3056 icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) icl_ddi_mg_pll_get_freq() argument
4311 intel_dpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) intel_dpll_get_freq() argument
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H A Dintel_cx0_phy.h29 void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c10pll_state *pll_state);
34 const struct intel_c10pll_state *pll_state);
38 struct intel_c20pll_state *pll_state);
42 const struct intel_c20pll_state *pll_state);
H A Dintel_snps_phy.c1824 const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state; in intel_mpllb_enable() local
1833 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); in intel_mpllb_enable()
1834 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); in intel_mpllb_enable()
1835 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); in intel_mpllb_enable()
1836 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); in intel_mpllb_enable()
1837 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); in intel_mpllb_enable()
1838 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); in intel_mpllb_enable()
1839 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); in intel_mpllb_enable()
1860 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); in intel_mpllb_enable()
1920 const struct intel_mpllb_state *pll_state) in intel_mpllb_calc_port_clock()
1919 intel_mpllb_calc_port_clock(struct intel_encoder *encoder, const struct intel_mpllb_state *pll_state) intel_mpllb_calc_port_clock() argument
1950 intel_mpllb_readout_hw_state(struct intel_encoder *encoder, struct intel_mpllb_state *pll_state) intel_mpllb_readout_hw_state() argument
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H A Dintel_snps_phy.h28 struct intel_mpllb_state *pll_state);
30 const struct intel_mpllb_state *pll_state);
H A Dintel_dpll_mgr.h347 const struct intel_dpll_hw_state *pll_state);
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c283 const struct intel_dpll_hw_state *pll_state, in intel_find_shared_dpll()
305 if (memcmp(pll_state, in intel_find_shared_dpll()
307 sizeof(*pll_state)) == 0) { in intel_find_shared_dpll()
333 const struct intel_dpll_hw_state *pll_state) in intel_reference_shared_dpll()
342 shared_dpll[id].hw_state = *pll_state; in intel_reference_shared_dpll()
1582 const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; in skl_ddi_wrpll_get_freq() local
1586 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; in skl_ddi_wrpll_get_freq()
1587 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; in skl_ddi_wrpll_get_freq()
1589 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) in skl_ddi_wrpll_get_freq()
1590 p1 = (pll_state in skl_ddi_wrpll_get_freq()
281 intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_dpll_hw_state *pll_state, unsigned long dpll_mask) intel_find_shared_dpll() argument
330 intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) intel_reference_shared_dpll() argument
2210 const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; bxt_ddi_pll_get_freq() local
2639 const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; __cnl_ddi_wrpll_get_freq() local
3068 icl_calc_dpll_state(struct drm_i915_private *i915, const struct skl_wrpll_params *pll_params, struct intel_dpll_hw_state *pll_state) icl_calc_dpll_state() argument
3183 icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, struct intel_dpll_hw_state *pll_state) icl_calc_mg_pll_state() argument
3391 const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; icl_ddi_mg_pll_get_freq() local
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/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-stm32f4.c667 int pll_state; in stm32f4_pll_set_rate() local
669 pll_state = stm32f4_pll_is_enabled(hw); in stm32f4_pll_set_rate()
671 if (pll_state) in stm32f4_pll_set_rate()
680 if (pll_state) in stm32f4_pll_set_rate()
717 int pll_state, ret; in stm32f4_pll_div_set_rate() local
722 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
724 if (pll_state) in stm32f4_pll_div_set_rate()
729 if (pll_state) in stm32f4_pll_div_set_rate()
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-stm32f4.c667 int pll_state; in stm32f4_pll_set_rate() local
669 pll_state = stm32f4_pll_is_enabled(hw); in stm32f4_pll_set_rate()
671 if (pll_state) in stm32f4_pll_set_rate()
680 if (pll_state) in stm32f4_pll_set_rate()
717 int pll_state, ret; in stm32f4_pll_div_set_rate() local
722 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
724 if (pll_state) in stm32f4_pll_div_set_rate()
729 if (pll_state) in stm32f4_pll_div_set_rate()
/kernel/linux/linux-5.10/sound/soc/codecs/
H A Dwm8580.c228 struct pll_state { struct
248 struct pll_state a;
249 struct pll_state b;
466 struct pll_state *state; in wm8580_set_dai_pll()
/kernel/linux/linux-6.6/sound/soc/codecs/
H A Dwm8580.c228 struct pll_state { struct
248 struct pll_state a;
249 struct pll_state b;
466 struct pll_state *state; in wm8580_set_dai_pll()

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