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Searched refs:pll_settings (Results 1 - 21 of 21) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c180 * @pll_settings: Pointer to PLL settings
193 struct pll_settings *pll_settings, in calc_fb_divider_checking_tolerance()
206 pll_settings->adjusted_pix_clk_100hz, in calc_fb_divider_checking_tolerance()
225 pll_settings->adjusted_pix_clk_100hz) in calc_fb_divider_checking_tolerance()
227 pll_settings->adjusted_pix_clk_100hz in calc_fb_divider_checking_tolerance()
228 : pll_settings->adjusted_pix_clk_100hz - in calc_fb_divider_checking_tolerance()
233 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; in calc_fb_divider_checking_tolerance()
234 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance()
235 pll_settings in calc_fb_divider_checking_tolerance()
191 calc_fb_divider_checking_tolerance( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings, uint32_t ref_divider, uint32_t post_divider, uint32_t tolerance) calc_fb_divider_checking_tolerance() argument
247 calc_pll_dividers_in_range( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings, uint32_t min_ref_divider, uint32_t max_ref_divider, uint32_t min_post_divider, uint32_t max_post_divider, uint32_t err_tolerance) calc_pll_dividers_in_range() argument
289 calculate_pixel_clock_pll_dividers( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings) calculate_pixel_clock_pll_dividers() argument
392 pll_adjust_pix_clk( struct dce110_clk_src *clk_src, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) pll_adjust_pix_clk() argument
471 dce110_get_pix_clk_dividers_helper( struct dce110_clk_src *clk_src, struct pll_settings *pll_settings, struct pixel_clk_params *pix_clk_params) dce110_get_pix_clk_dividers_helper() argument
533 dce112_get_pix_clk_dividers_helper( struct dce110_clk_src *clk_src, struct pll_settings *pll_settings, struct pixel_clk_params *pix_clk_params) dce112_get_pix_clk_dividers_helper() argument
564 dce110_get_pix_clk_dividers( struct clock_source *cs, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dce110_get_pix_clk_dividers() argument
597 dce112_get_pix_clk_dividers( struct clock_source *cs, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dce112_get_pix_clk_dividers() argument
645 calculate_ss( const struct pll_settings *pll_settings, const struct spread_spectrum_data *ss_data, struct delta_sigma_data *ds_data) calculate_ss() argument
710 enable_spread_spectrum( struct dce110_clk_src *clk_src, enum signal_type signal, struct pll_settings *pll_settings) enable_spread_spectrum() argument
840 dce110_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) dce110_program_pix_clk() argument
914 dce112_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) dce112_program_pix_clk() argument
961 dcn31_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) dcn31_program_pix_clk() argument
1167 dcn20_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) dcn20_program_pix_clk() argument
1213 dcn3_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, enum dp_link_encoding encoding, struct pll_settings *pll_settings) dcn3_program_pix_clk() argument
1251 dcn3_get_pix_clk_dividers( struct clock_source *cs, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dcn3_get_pix_clk_dividers() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c183 * pll_settings Pointer to structure
196 struct pll_settings *pll_settings, in calc_fb_divider_checking_tolerance()
209 pll_settings->adjusted_pix_clk_100hz, in calc_fb_divider_checking_tolerance()
228 pll_settings->adjusted_pix_clk_100hz) in calc_fb_divider_checking_tolerance()
230 pll_settings->adjusted_pix_clk_100hz in calc_fb_divider_checking_tolerance()
231 : pll_settings->adjusted_pix_clk_100hz - in calc_fb_divider_checking_tolerance()
236 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; in calc_fb_divider_checking_tolerance()
237 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance()
238 pll_settings in calc_fb_divider_checking_tolerance()
194 calc_fb_divider_checking_tolerance( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings, uint32_t ref_divider, uint32_t post_divider, uint32_t tolerance) calc_fb_divider_checking_tolerance() argument
250 calc_pll_dividers_in_range( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings, uint32_t min_ref_divider, uint32_t max_ref_divider, uint32_t min_post_divider, uint32_t max_post_divider, uint32_t err_tolerance) calc_pll_dividers_in_range() argument
292 calculate_pixel_clock_pll_dividers( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings) calculate_pixel_clock_pll_dividers() argument
395 pll_adjust_pix_clk( struct dce110_clk_src *clk_src, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) pll_adjust_pix_clk() argument
474 dce110_get_pix_clk_dividers_helper( struct dce110_clk_src *clk_src, struct pll_settings *pll_settings, struct pixel_clk_params *pix_clk_params) dce110_get_pix_clk_dividers_helper() argument
536 dce112_get_pix_clk_dividers_helper( struct dce110_clk_src *clk_src, struct pll_settings *pll_settings, struct pixel_clk_params *pix_clk_params) dce112_get_pix_clk_dividers_helper() argument
567 dce110_get_pix_clk_dividers( struct clock_source *cs, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dce110_get_pix_clk_dividers() argument
600 dce112_get_pix_clk_dividers( struct clock_source *cs, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dce112_get_pix_clk_dividers() argument
648 calculate_ss( const struct pll_settings *pll_settings, const struct spread_spectrum_data *ss_data, struct delta_sigma_data *ds_data) calculate_ss() argument
713 enable_spread_spectrum( struct dce110_clk_src *clk_src, enum signal_type signal, struct pll_settings *pll_settings) enable_spread_spectrum() argument
843 dce110_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dce110_program_pix_clk() argument
916 dce112_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dce112_program_pix_clk() argument
1075 dcn20_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dcn20_program_pix_clk() argument
1093 dcn3_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dcn3_program_pix_clk() argument
1123 dcn3_get_pix_clk_dividers( struct clock_source *cs, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) dcn3_get_pix_clk_dividers() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h106 struct pll_settings { struct
164 struct pixel_clk_params *, struct pll_settings *);
168 struct pll_settings *);
H A Dcore_types.h317 struct pll_settings pll_settings; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h106 struct pll_settings { struct
167 struct pll_settings *);
171 struct pll_settings *);
H A Dcore_types.h376 struct pll_settings pll_settings; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_hwseq.c462 &pipe_ctx->pll_settings); in apply_symclk_on_tx_off_wa()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_hwss.c128 &pipes[i].pll_settings); in dp_enable_link_phy()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c1254 pipe_ctx->pll_settings.feedback_divider; in build_audio_output()
1264 pipe_ctx->pll_settings.ss_percentage; in build_audio_output()
1371 &pipe_ctx->pll_settings)) { in dce110_enable_stream_timing()
H A Ddce110_resource.c930 &pipe_ctx->pll_settings); in dce110_resource_build_pipe_hw_param()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c1359 pipe_ctx->pll_settings.feedback_divider; in build_audio_output()
1369 pipe_ctx->pll_settings.ss_percentage; in build_audio_output()
1440 &pipe_ctx->pll_settings)) { in dce110_enable_stream_timing()
3083 &pipes[i].pll_settings); in dce110_enable_dp_link_output()
H A Ddce110_resource.c923 &pipe_ctx->pll_settings); in dce110_resource_build_pipe_hw_param()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_resource.c1108 &pipe_ctx->pll_settings); in build_pipe_hw_param()
H A Ddcn10_hw_sequencer.c808 &pipe_ctx->pll_settings)) { in dcn10_enable_stream_timing()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_resource.c1044 &pipe_ctx->pll_settings); in build_pipe_hw_param()
H A Ddcn10_hw_sequencer.c928 &pipe_ctx->pll_settings)) { in dcn10_enable_stream_timing()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.c1310 &pipe_ctx->pll_settings); in apply_symclk_on_tx_off_wa()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hwseq.c689 &pipe_ctx->pll_settings)) { in dcn20_enable_stream_timing()
H A Ddcn20_resource.c1641 &pipe_ctx->pll_settings); in build_pipe_hw_param()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1283 &pipe_ctx->pll_settings); in build_pipe_hw_param()
H A Ddcn20_hwseq.c728 &pipe_ctx->pll_settings)) { in dcn20_enable_stream_timing()

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