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Searched refs:pll_mux (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/rockchip/
H A Dclk-pll.c29 struct clk_mux pll_mux; member
193 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_set_params() local
207 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3036_pll_set_params()
209 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
428 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_params() local
440 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3066_pll_set_params()
442 pll_mux_ops->set_parent(&pll_mux in rockchip_rk3066_pll_set_params()
675 struct clk_mux *pll_mux = &pll->pll_mux; rockchip_rk3399_pll_set_params() local
860 struct clk_mux *pll_mux; rockchip_clk_register_pll() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/rockchip/
H A Dclk-pll.c29 struct clk_mux pll_mux; member
193 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_set_params() local
207 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3036_pll_set_params()
209 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
428 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_params() local
440 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3066_pll_set_params()
442 pll_mux_ops->set_parent(&pll_mux in rockchip_rk3066_pll_set_params()
675 struct clk_mux *pll_mux = &pll->pll_mux; rockchip_rk3399_pll_set_params() local
924 struct clk_mux *pll_mux = &pll->pll_mux; rockchip_rk3588_pll_set_params() local
1067 struct clk_mux *pll_mux; rockchip_clk_register_pll() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/socfpga/
H A Dclk-agilex.c15 static const struct clk_parent_data pll_mux[] = { variable
228 { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
230 { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
H A Dclk-s10.c15 static const struct clk_parent_data pll_mux[] = { variable
186 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
188 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
/kernel/linux/linux-6.6/drivers/clk/socfpga/
H A Dclk-agilex.c14 static const struct clk_parent_data pll_mux[] = { variable
229 { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
231 { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
H A Dclk-s10.c14 static const struct clk_parent_data pll_mux[] = { variable
185 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
187 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/
H A Ddsi_pll_10nm.c84 u8 pll_mux; member
549 cached->pll_mux = cmn_clk_cfg1 & 0x3; in dsi_pll_10nm_save_state()
551 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", in dsi_pll_10nm_save_state()
553 cached->pix_clk_div, cached->pll_mux); in dsi_pll_10nm_save_state()
574 val |= cached->pll_mux; in dsi_pll_10nm_restore_state()
H A Ddsi_pll_7nm.c84 u8 pll_mux; member
575 cached->pll_mux = cmn_clk_cfg1 & 0x3; in dsi_pll_7nm_save_state()
577 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", in dsi_pll_7nm_save_state()
579 cached->pix_clk_div, cached->pll_mux); in dsi_pll_7nm_save_state()
600 val |= cached->pll_mux; in dsi_pll_7nm_restore_state()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c66 u8 pll_mux; member
500 cached->pll_mux = cmn_clk_cfg1 & 0x3; in dsi_10nm_pll_save_state()
502 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", in dsi_10nm_pll_save_state()
504 cached->pix_clk_div, cached->pll_mux); in dsi_10nm_pll_save_state()
525 val |= cached->pll_mux; in dsi_10nm_pll_restore_state()
H A Ddsi_phy_7nm.c73 u8 pll_mux; member
549 cached->pll_mux = cmn_clk_cfg1 & 0x3; in dsi_7nm_pll_save_state()
551 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x", in dsi_7nm_pll_save_state()
553 cached->pix_clk_div, cached->pll_mux); in dsi_7nm_pll_save_state()
574 val |= cached->pll_mux; in dsi_7nm_pll_restore_state()

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