| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_encoder_phys_cmd.c | 39 static void dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc);
41 static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_cmd_is_master() argument
43 return (phys_enc->split_role != ENC_ROLE_SLAVE); in dpu_encoder_phys_cmd_is_master()
47 struct dpu_encoder_phys *phys_enc) in _dpu_encoder_phys_cmd_update_intf_cfg()
50 to_dpu_encoder_phys_cmd(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
55 ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_cmd_update_intf_cfg()
59 intf_cfg.intf = phys_enc->hw_intf->idx; in _dpu_encoder_phys_cmd_update_intf_cfg()
62 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
63 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
67 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc in _dpu_encoder_phys_cmd_update_intf_cfg()
46 _dpu_encoder_phys_cmd_update_intf_cfg( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_update_intf_cfg() argument
81 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_cmd_pp_tx_done_irq() local
108 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_cmd_te_rd_ptr_irq() local
131 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_cmd_ctl_start_irq() local
144 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_cmd_underrun_irq() local
149 dpu_encoder_phys_cmd_atomic_mode_set( struct dpu_encoder_phys *phys_enc, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) dpu_encoder_phys_cmd_atomic_mode_set() argument
166 _dpu_encoder_phys_cmd_handle_ppdone_timeout( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_handle_ppdone_timeout() argument
217 _dpu_encoder_phys_cmd_wait_for_idle( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_wait_for_idle() argument
241 dpu_encoder_phys_cmd_control_vblank_irq( struct dpu_encoder_phys *phys_enc, bool enable) dpu_encoder_phys_cmd_control_vblank_irq() argument
289 dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, bool enable) dpu_encoder_phys_cmd_irq_control() argument
325 dpu_encoder_phys_cmd_tearcheck_config( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_tearcheck_config() argument
409 _dpu_encoder_phys_cmd_pingpong_config( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_pingpong_config() argument
428 dpu_encoder_phys_cmd_needs_single_flush( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_needs_single_flush() argument
438 dpu_encoder_phys_cmd_enable_helper( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_enable_helper() argument
459 dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_enable() argument
480 _dpu_encoder_phys_cmd_connect_te( struct dpu_encoder_phys *phys_enc, bool enable) _dpu_encoder_phys_cmd_connect_te() argument
498 dpu_encoder_phys_cmd_prepare_idle_pc( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_prepare_idle_pc() argument
504 dpu_encoder_phys_cmd_get_line_count( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_get_line_count() argument
526 dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_disable() argument
570 dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_destroy() argument
578 dpu_encoder_phys_cmd_prepare_for_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_prepare_for_kickoff() argument
613 dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_enable_te() argument
640 _dpu_encoder_phys_cmd_wait_for_ctl_start( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_wait_for_ctl_start() argument
665 dpu_encoder_phys_cmd_wait_for_tx_complete( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_wait_for_tx_complete() argument
680 dpu_encoder_phys_cmd_wait_for_commit_done( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_wait_for_commit_done() argument
693 dpu_encoder_phys_cmd_wait_for_vblank( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_wait_for_vblank() argument
720 dpu_encoder_phys_cmd_handle_post_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_handle_post_kickoff() argument
730 dpu_encoder_phys_cmd_trigger_start( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_trigger_start() argument
761 struct dpu_encoder_phys *phys_enc = NULL; dpu_encoder_phys_cmd_init() local
[all...] |
| H A D | dpu_encoder_phys_vid.c | 30 struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_vid_is_master()
34 if (phys_enc->split_role != ENC_ROLE_SLAVE) in dpu_encoder_phys_vid_is_master()
41 const struct dpu_encoder_phys *phys_enc, in drm_mode_to_intf_timing_params()
89 if (phys_enc->hw_intf->cap->type == INTF_DSI) { in drm_mode_to_intf_timing_params()
95 if (phys_enc->hw_intf->cap->type == INTF_DP) { in drm_mode_to_intf_timing_params()
102 timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent); in drm_mode_to_intf_timing_params()
103 timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent); in drm_mode_to_intf_timing_params()
109 if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) { in drm_mode_to_intf_timing_params()
151 struct dpu_encoder_phys *phys_enc, in programmable_fetch_get_num_lines()
155 phys_enc in programmable_fetch_get_num_lines()
29 dpu_encoder_phys_vid_is_master( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_is_master() argument
40 drm_mode_to_intf_timing_params( const struct dpu_encoder_phys *phys_enc, const struct drm_display_mode *mode, struct dpu_hw_intf_timing_params *timing) drm_mode_to_intf_timing_params() argument
150 programmable_fetch_get_num_lines( struct dpu_encoder_phys *phys_enc, const struct dpu_hw_intf_timing_params *timing) programmable_fetch_get_num_lines() argument
199 programmable_fetch_config(struct dpu_encoder_phys *phys_enc, const struct dpu_hw_intf_timing_params *timing) programmable_fetch_config() argument
231 dpu_encoder_phys_vid_setup_timing_engine( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_setup_timing_engine() argument
305 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_vid_vblank_irq() local
342 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_vid_underrun_irq() local
347 dpu_encoder_phys_vid_needs_single_flush( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_needs_single_flush() argument
353 dpu_encoder_phys_vid_atomic_mode_set( struct dpu_encoder_phys *phys_enc, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) dpu_encoder_phys_vid_atomic_mode_set() argument
363 dpu_encoder_phys_vid_control_vblank_irq( struct dpu_encoder_phys *phys_enc, bool enable) dpu_encoder_phys_vid_control_vblank_irq() argument
404 dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_enable() argument
444 dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_destroy() argument
450 dpu_encoder_phys_vid_wait_for_vblank( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_wait_for_vblank() argument
477 dpu_encoder_phys_vid_wait_for_commit_done( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_wait_for_commit_done() argument
497 dpu_encoder_phys_vid_prepare_for_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_prepare_for_kickoff() argument
524 dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_disable() argument
597 dpu_encoder_phys_vid_handle_post_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_handle_post_kickoff() argument
616 dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, bool enable) dpu_encoder_phys_vid_irq_control() argument
642 dpu_encoder_phys_vid_get_line_count( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_get_line_count() argument
654 dpu_encoder_phys_vid_get_frame_count( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_get_frame_count() argument
703 struct dpu_encoder_phys *phys_enc = NULL; dpu_encoder_phys_vid_init() local
[all...] |
| H A D | dpu_encoder_phys_wb.c | 29 * @phys_enc: Pointer to physical encoder
31 static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_wb_is_master() argument
39 * @phys_enc: Pointer to physical encoder
42 struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_wb_set_ot_limit()
44 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb; in dpu_encoder_phys_wb_set_ot_limit()
50 ot_params.width = phys_enc->cached_mode.hdisplay; in dpu_encoder_phys_wb_set_ot_limit()
51 ot_params.height = phys_enc->cached_mode.vdisplay; in dpu_encoder_phys_wb_set_ot_limit()
53 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode); in dpu_encoder_phys_wb_set_ot_limit()
58 dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params); in dpu_encoder_phys_wb_set_ot_limit()
63 * @phys_enc
41 dpu_encoder_phys_wb_set_ot_limit( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_set_ot_limit() argument
65 dpu_encoder_phys_wb_set_qos_remap( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_set_qos_remap() argument
102 dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_set_qos() argument
137 dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, struct drm_framebuffer *fb) dpu_encoder_phys_wb_setup_fb() argument
179 dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_setup_cdp() argument
234 dpu_encoder_phys_wb_atomic_check( struct dpu_encoder_phys *phys_enc, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) dpu_encoder_phys_wb_atomic_check() argument
285 _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_wb_update_flush() argument
325 dpu_encoder_phys_wb_setup( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_setup() argument
350 struct dpu_encoder_phys *phys_enc = arg; _dpu_encoder_phys_wb_frame_done_helper() local
403 dpu_encoder_phys_wb_atomic_mode_set( struct dpu_encoder_phys *phys_enc, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) dpu_encoder_phys_wb_atomic_mode_set() argument
412 _dpu_encoder_phys_wb_handle_wbdone_timeout( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_wb_handle_wbdone_timeout() argument
438 dpu_encoder_phys_wb_wait_for_commit_done( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_wait_for_commit_done() argument
465 dpu_encoder_phys_wb_prepare_for_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_prepare_for_kickoff() argument
494 dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_needs_single_flush() argument
504 dpu_encoder_phys_wb_handle_post_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_handle_post_kickoff() argument
515 dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_enable() argument
524 dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_disable() argument
560 dpu_encoder_phys_wb_destroy(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_destroy() argument
570 dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc, struct drm_writeback_job *job) dpu_encoder_phys_wb_prepare_wb_job() argument
629 dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc, struct drm_writeback_job *job) dpu_encoder_phys_wb_cleanup_wb_job() argument
645 dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_wb_is_valid_for_commit() argument
686 struct dpu_encoder_phys *phys_enc = NULL; dpu_encoder_phys_wb_init() local
[all...] |
| H A D | dpu_encoder_phys.h | 67 * @is_master: Whether this phys_enc is the current master
107 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
108 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
109 int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
110 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
111 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
112 void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
113 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
115 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
119 void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc,
310 dpu_encoder_helper_get_3d_blend_mode( struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_get_3d_blend_mode() argument
[all...] |
| H A D | dpu_encoder.c | 136 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
151 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
342 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_report_irq_timeout() argument
346 DRMID(phys_enc->parent), in dpu_encoder_helper_report_irq_timeout()
347 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode), in dpu_encoder_helper_report_irq_timeout()
348 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, in dpu_encoder_helper_report_irq_timeout()
349 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1, in dpu_encoder_helper_report_irq_timeout()
350 phys_enc in dpu_encoder_helper_report_irq_timeout()
359 dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, int irq, void (*func)(void *arg, int irq_idx), struct dpu_encoder_wait_info *wait_info) dpu_encoder_helper_wait_for_irq() argument
487 dpu_encoder_helper_split_config( struct dpu_encoder_phys *phys_enc, enum dpu_intf interface) dpu_encoder_helper_split_config() argument
692 struct dpu_encoder_phys *phys_enc; _dpu_encoder_update_vsync_source() local
1537 dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_trigger_start() argument
1573 dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_hw_reset() argument
1968 dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_reset_mixers() argument
2034 dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_phys_cleanup() argument
2484 dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_get_dsc() argument
2492 dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, struct dpu_enc_phys_init_params *p) dpu_encoder_phys_init() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_encoder_phys_cmd.c | 38 static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_cmd_is_master() argument
40 return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false; in dpu_encoder_phys_cmd_is_master()
44 struct dpu_encoder_phys *phys_enc, in dpu_encoder_phys_cmd_mode_fixup()
48 DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n"); in dpu_encoder_phys_cmd_mode_fixup()
53 struct dpu_encoder_phys *phys_enc) in _dpu_encoder_phys_cmd_update_intf_cfg()
56 to_dpu_encoder_phys_cmd(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
60 ctl = phys_enc->hw_ctl; in _dpu_encoder_phys_cmd_update_intf_cfg()
64 intf_cfg.intf = phys_enc->intf_idx; in _dpu_encoder_phys_cmd_update_intf_cfg()
67 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
73 struct dpu_encoder_phys *phys_enc in dpu_encoder_phys_cmd_pp_tx_done_irq() local
43 dpu_encoder_phys_cmd_mode_fixup( struct dpu_encoder_phys *phys_enc, const struct drm_display_mode *mode, struct drm_display_mode *adj_mode) dpu_encoder_phys_cmd_mode_fixup() argument
52 _dpu_encoder_phys_cmd_update_intf_cfg( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_update_intf_cfg() argument
102 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_cmd_pp_rd_ptr_irq() local
122 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_cmd_ctl_start_irq() local
135 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_cmd_underrun_irq() local
142 _dpu_encoder_phys_cmd_setup_irq_hw_idx( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_setup_irq_hw_idx() argument
164 dpu_encoder_phys_cmd_mode_set( struct dpu_encoder_phys *phys_enc, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) dpu_encoder_phys_cmd_mode_set() argument
183 _dpu_encoder_phys_cmd_handle_ppdone_timeout( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_handle_ppdone_timeout() argument
232 _dpu_encoder_phys_cmd_wait_for_idle( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_wait_for_idle() argument
254 dpu_encoder_phys_cmd_control_vblank_irq( struct dpu_encoder_phys *phys_enc, bool enable) dpu_encoder_phys_cmd_control_vblank_irq() argument
299 dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, bool enable) dpu_encoder_phys_cmd_irq_control() argument
325 dpu_encoder_phys_cmd_tearcheck_config( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_tearcheck_config() argument
407 _dpu_encoder_phys_cmd_pingpong_config( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_pingpong_config() argument
426 dpu_encoder_phys_cmd_needs_single_flush( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_needs_single_flush() argument
436 dpu_encoder_phys_cmd_enable_helper( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_enable_helper() argument
459 dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_enable() argument
480 _dpu_encoder_phys_cmd_connect_te( struct dpu_encoder_phys *phys_enc, bool enable) _dpu_encoder_phys_cmd_connect_te() argument
490 dpu_encoder_phys_cmd_prepare_idle_pc( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_prepare_idle_pc() argument
496 dpu_encoder_phys_cmd_get_line_count( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_get_line_count() argument
514 dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_disable() argument
537 dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_destroy() argument
545 dpu_encoder_phys_cmd_get_hw_resources( struct dpu_encoder_phys *phys_enc, struct dpu_encoder_hw_resources *hw_res) dpu_encoder_phys_cmd_get_hw_resources() argument
552 dpu_encoder_phys_cmd_prepare_for_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_prepare_for_kickoff() argument
585 _dpu_encoder_phys_cmd_wait_for_ctl_start( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_cmd_wait_for_ctl_start() argument
608 dpu_encoder_phys_cmd_wait_for_tx_complete( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_wait_for_tx_complete() argument
623 dpu_encoder_phys_cmd_wait_for_commit_done( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_wait_for_commit_done() argument
642 dpu_encoder_phys_cmd_wait_for_vblank( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_wait_for_vblank() argument
667 dpu_encoder_phys_cmd_handle_post_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_handle_post_kickoff() argument
677 dpu_encoder_phys_cmd_trigger_start( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_cmd_trigger_start() argument
710 struct dpu_encoder_phys *phys_enc = NULL; dpu_encoder_phys_cmd_init() local
[all...] |
| H A D | dpu_encoder_phys_vid.c | 28 struct dpu_encoder_phys *phys_enc) in dpu_encoder_phys_vid_is_master()
32 if (phys_enc->split_role != ENC_ROLE_SLAVE) in dpu_encoder_phys_vid_is_master()
39 const struct dpu_encoder_phys *phys_enc, in drm_mode_to_intf_timing_params()
87 if (phys_enc->hw_intf->cap->type == INTF_DSI) { in drm_mode_to_intf_timing_params()
104 if ((phys_enc->hw_intf->cap->type == INTF_DP) || in drm_mode_to_intf_timing_params()
105 (phys_enc->hw_intf->cap->type == INTF_EDP)) { in drm_mode_to_intf_timing_params()
146 struct dpu_encoder_phys *phys_enc, in programmable_fetch_get_num_lines()
150 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; in programmable_fetch_get_num_lines()
158 DPU_DEBUG_VIDENC(phys_enc, in programmable_fetch_get_num_lines()
165 DPU_DEBUG_VIDENC(phys_enc, in programmable_fetch_get_num_lines()
27 dpu_encoder_phys_vid_is_master( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_is_master() argument
38 drm_mode_to_intf_timing_params( const struct dpu_encoder_phys *phys_enc, const struct drm_display_mode *mode, struct intf_timing_params *timing) drm_mode_to_intf_timing_params() argument
145 programmable_fetch_get_num_lines( struct dpu_encoder_phys *phys_enc, const struct intf_timing_params *timing) programmable_fetch_get_num_lines() argument
194 programmable_fetch_config(struct dpu_encoder_phys *phys_enc, const struct intf_timing_params *timing) programmable_fetch_config() argument
226 dpu_encoder_phys_vid_mode_fixup( struct dpu_encoder_phys *phys_enc, const struct drm_display_mode *mode, struct drm_display_mode *adj_mode) dpu_encoder_phys_vid_mode_fixup() argument
239 dpu_encoder_phys_vid_setup_timing_engine( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_setup_timing_engine() argument
305 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_vid_vblank_irq() local
344 struct dpu_encoder_phys *phys_enc = arg; dpu_encoder_phys_vid_underrun_irq() local
351 dpu_encoder_phys_vid_needs_single_flush( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_needs_single_flush() argument
357 _dpu_encoder_phys_vid_setup_irq_hw_idx( struct dpu_encoder_phys *phys_enc) _dpu_encoder_phys_vid_setup_irq_hw_idx() argument
377 dpu_encoder_phys_vid_mode_set( struct dpu_encoder_phys *phys_enc, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) dpu_encoder_phys_vid_mode_set() argument
391 dpu_encoder_phys_vid_control_vblank_irq( struct dpu_encoder_phys *phys_enc, bool enable) dpu_encoder_phys_vid_control_vblank_irq() argument
429 dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_enable() argument
476 dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_destroy() argument
482 dpu_encoder_phys_vid_get_hw_resources( struct dpu_encoder_phys *phys_enc, struct dpu_encoder_hw_resources *hw_res) dpu_encoder_phys_vid_get_hw_resources() argument
489 dpu_encoder_phys_vid_wait_for_vblank( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_wait_for_vblank() argument
514 dpu_encoder_phys_vid_wait_for_commit_done( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_wait_for_commit_done() argument
534 dpu_encoder_phys_vid_prepare_for_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_prepare_for_kickoff() argument
556 dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_disable() argument
607 dpu_encoder_phys_vid_handle_post_kickoff( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_handle_post_kickoff() argument
626 dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, bool enable) dpu_encoder_phys_vid_irq_control() argument
648 dpu_encoder_phys_vid_get_line_count( struct dpu_encoder_phys *phys_enc) dpu_encoder_phys_vid_get_line_count() argument
683 struct dpu_encoder_phys *phys_enc = NULL; dpu_encoder_phys_vid_init() local
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| H A D | dpu_encoder_phys.h | 84 * @is_master: Whether this phys_enc is the current master
95 * resources that this phys_enc is using.
135 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
136 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
137 int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
138 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
139 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
140 void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
141 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
143 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
321 dpu_encoder_helper_get_3d_blend_mode( struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_get_3d_blend_mode() argument
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| H A D | dpu_encoder.c | 140 * @intfs_swapped Whether or not the phys_enc interfaces have been swapped
154 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
244 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, in dpu_encoder_helper_report_irq_timeout() argument
248 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, in dpu_encoder_helper_report_irq_timeout()
249 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); in dpu_encoder_helper_report_irq_timeout()
251 if (phys_enc->parent_ops->handle_frame_done) in dpu_encoder_helper_report_irq_timeout()
252 phys_enc->parent_ops->handle_frame_done( in dpu_encoder_helper_report_irq_timeout()
253 phys_enc->parent, phys_enc, in dpu_encoder_helper_report_irq_timeout()
260 dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, enum dpu_intr_idx intr_idx, struct dpu_encoder_wait_info *wait_info) dpu_encoder_helper_wait_for_irq() argument
337 dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, enum dpu_intr_idx intr_idx) dpu_encoder_helper_register_irq() argument
392 dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, enum dpu_intr_idx intr_idx) dpu_encoder_helper_unregister_irq() argument
486 dpu_encoder_helper_split_config( struct dpu_encoder_phys *phys_enc, enum dpu_intf interface) dpu_encoder_helper_split_config() argument
1507 dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_trigger_start() argument
1543 dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_hw_reset() argument
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