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Searched refs:pending_limit (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_if.c30 * @pending_limit: the maximum pending interrupt events (unit 8)
39 u8 pending_limit, u8 coalesc_timer, in hinic_msix_attr_set()
48 msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | in hinic_msix_attr_set()
64 * @pending_limit: the maximum pending interrupt events (unit 8)
73 u8 *pending_limit, u8 *coalesc_timer, in hinic_msix_attr_get()
85 *pending_limit = HINIC_MSIX_ATTR_GET(val, PENDING_LIMIT); in hinic_msix_attr_get()
38 hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, u8 pending_limit, u8 coalesc_timer, u8 lli_timer, u8 lli_credit_limit, u8 resend_timer) hinic_msix_attr_set() argument
72 hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index, u8 *pending_limit, u8 *coalesc_timer, u8 *lli_timer, u8 *lli_credit_limit, u8 *resend_timer) hinic_msix_attr_get() argument
H A Dhinic_hw_dev.h285 u8 pending_limit; member
580 u8 pending_limit, u8 coalesc_timer,
585 u8 pending_limit, u8 coalesc_timer);
H A Dhinic_hw_if.h268 u8 pending_limit, u8 coalesc_timer,
273 u8 *pending_limit, u8 *coalesc_timer_cfg,
H A Dhinic_hw_dev.c1125 * @pending_limit: the maximum pending interrupt events (unit 8)
1134 u8 pending_limit, u8 coalesc_timer, in hinic_hwdev_msix_set()
1139 pending_limit, coalesc_timer, in hinic_hwdev_msix_set()
1148 * @pending_limit: the maximum pending update ci events (unit 8)
1154 u8 pending_limit, u8 coalesc_timer) in hinic_hwdev_hw_ci_addr_set()
1162 hw_ci.pending_limit = pending_limit; in hinic_hwdev_hw_ci_addr_set()
1133 hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, u8 pending_limit, u8 coalesc_timer, u8 lli_timer_cfg, u8 lli_credit_limit, u8 resend_timer) hinic_hwdev_msix_set() argument
1153 hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, u8 pending_limit, u8 coalesc_timer) hinic_hwdev_hw_ci_addr_set() argument
/kernel/linux/linux-6.6/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_dev.c1103 * @pending_limit: the maximum pending interrupt events (unit 8)
1112 u8 pending_limit, u8 coalesc_timer, in hinic_hwdev_msix_set()
1117 pending_limit, coalesc_timer, in hinic_hwdev_msix_set()
1126 * @pending_limit: the maximum pending update ci events (unit 8)
1132 u8 pending_limit, u8 coalesc_timer) in hinic_hwdev_hw_ci_addr_set()
1140 hw_ci.pending_limit = pending_limit; in hinic_hwdev_hw_ci_addr_set()
1111 hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, u8 pending_limit, u8 coalesc_timer, u8 lli_timer_cfg, u8 lli_credit_limit, u8 resend_timer) hinic_hwdev_msix_set() argument
1131 hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, u8 pending_limit, u8 coalesc_timer) hinic_hwdev_hw_ci_addr_set() argument
H A Dhinic_hw_dev.h351 u8 pending_limit; member
644 u8 pending_limit, u8 coalesc_timer,
649 u8 pending_limit, u8 coalesc_timer);
H A Dhinic_hw_if.c30 * @pending_limit: the maximum pending interrupt events (unit 8)
39 u8 pending_limit, u8 coalesc_timer, in hinic_msix_attr_set()
48 msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | in hinic_msix_attr_set()
38 hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, u8 pending_limit, u8 coalesc_timer, u8 lli_timer, u8 lli_credit_limit, u8 resend_timer) hinic_msix_attr_set() argument
H A Dhinic_hw_if.h264 u8 pending_limit, u8 coalesc_timer,

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