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Searched refs:pad_mii_tx (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c368 struct sja1105_cfg_pad_mii pad_mii_tx = {0}; in sja1105_rgmii_cfg_pad_tx_config() local
372 pad_mii_tx.d32_os = 3; /* TXD[3:2] output stage: */ in sja1105_rgmii_cfg_pad_tx_config()
374 pad_mii_tx.d10_os = 3; /* TXD[1:0] output stage: */ in sja1105_rgmii_cfg_pad_tx_config()
376 pad_mii_tx.d32_ipud = 2; /* TXD[3:2] input stage: */ in sja1105_rgmii_cfg_pad_tx_config()
378 pad_mii_tx.d10_ipud = 2; /* TXD[1:0] input stage: */ in sja1105_rgmii_cfg_pad_tx_config()
380 pad_mii_tx.ctrl_os = 3; /* TX_CTL / TX_ER output stage */ in sja1105_rgmii_cfg_pad_tx_config()
381 pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
382 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ in sja1105_rgmii_cfg_pad_tx_config()
383 pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */ in sja1105_rgmii_cfg_pad_tx_config()
384 pad_mii_tx in sja1105_rgmii_cfg_pad_tx_config()
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H A Dsja1105_spi.c445 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
479 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
H A Dsja1105.h53 u64 pad_mii_tx[SJA1105_NUM_PORTS]; member
/kernel/linux/linux-6.6/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c394 struct sja1105_cfg_pad_mii pad_mii_tx = {0}; in sja1105_rgmii_cfg_pad_tx_config() local
397 if (regs->pad_mii_tx[port] == SJA1105_RSV_ADDR) in sja1105_rgmii_cfg_pad_tx_config()
401 pad_mii_tx.d32_os = 3; /* TXD[3:2] output stage: */ in sja1105_rgmii_cfg_pad_tx_config()
403 pad_mii_tx.d10_os = 3; /* TXD[1:0] output stage: */ in sja1105_rgmii_cfg_pad_tx_config()
405 pad_mii_tx.d32_ipud = 2; /* TXD[3:2] input stage: */ in sja1105_rgmii_cfg_pad_tx_config()
407 pad_mii_tx.d10_ipud = 2; /* TXD[1:0] input stage: */ in sja1105_rgmii_cfg_pad_tx_config()
409 pad_mii_tx.ctrl_os = 3; /* TX_CTL / TX_ER output stage */ in sja1105_rgmii_cfg_pad_tx_config()
410 pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
411 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ in sja1105_rgmii_cfg_pad_tx_config()
412 pad_mii_tx in sja1105_rgmii_cfg_pad_tx_config()
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H A Dsja1105_spi.c420 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
456 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
497 .pad_mii_tx = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
H A Dsja1105.h79 u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS]; member

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