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Searched refs:optimal (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/drivers/cpufreq/
H A Dfreq_table.c122 struct cpufreq_frequency_table optimal = { in cpufreq_table_index_unsorted() local
144 optimal.frequency = ~0; in cpufreq_table_index_unsorted()
154 optimal.driver_data = i; in cpufreq_table_index_unsorted()
160 if (freq >= optimal.frequency) { in cpufreq_table_index_unsorted()
161 optimal.frequency = freq; in cpufreq_table_index_unsorted()
162 optimal.driver_data = i; in cpufreq_table_index_unsorted()
173 if (freq <= optimal.frequency) { in cpufreq_table_index_unsorted()
174 optimal.frequency = freq; in cpufreq_table_index_unsorted()
175 optimal.driver_data = i; in cpufreq_table_index_unsorted()
186 if (diff < optimal in cpufreq_table_index_unsorted()
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/kernel/linux/linux-6.6/drivers/cpufreq/
H A Dfreq_table.c122 struct cpufreq_frequency_table optimal = { in cpufreq_table_index_unsorted() local
144 optimal.frequency = ~0; in cpufreq_table_index_unsorted()
154 optimal.driver_data = i; in cpufreq_table_index_unsorted()
160 if (freq >= optimal.frequency) { in cpufreq_table_index_unsorted()
161 optimal.frequency = freq; in cpufreq_table_index_unsorted()
162 optimal.driver_data = i; in cpufreq_table_index_unsorted()
173 if (freq <= optimal.frequency) { in cpufreq_table_index_unsorted()
174 optimal.frequency = freq; in cpufreq_table_index_unsorted()
175 optimal.driver_data = i; in cpufreq_table_index_unsorted()
186 if (diff < optimal in cpufreq_table_index_unsorted()
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Di9xx_wm.c1108 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in _g4x_compute_pipe_wm()
1202 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm() local
1203 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1208 *intermediate = *optimal; in g4x_compute_intermediate_wm()
1215 intermediate->cxsr = optimal->cxsr && active->cxsr && in g4x_compute_intermediate_wm()
1217 intermediate->hpll_en = optimal->hpll_en && active->hpll_en && in g4x_compute_intermediate_wm()
1219 intermediate->fbc_en = optimal->fbc_en && active->fbc_en; in g4x_compute_intermediate_wm()
1223 max(optimal->wm.plane[plane_id], in g4x_compute_intermediate_wm()
1230 intermediate->sr.plane = max(optimal in g4x_compute_intermediate_wm()
1857 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal; vlv_compute_intermediate_wm() local
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H A Dskl_watermark.c356 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
378 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
401 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
483 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; in intel_compute_sagv_mask()
1532 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1580 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1611 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
1639 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_allocate_plane_ddb()
2229 const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_max_wm0_lines()
2290 &crtc_state->wm.skl.optimal in skl_wm_check_vblank()
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H A Dintel_display_types.h913 * optimal:
914 * The "optimal" watermark values given the current
921 * between the old and new "optimal" values. Used when
925 * worst case combination of the old and new "optimal"
931 struct intel_pipe_wm optimal; member
937 struct skl_pipe_wm optimal; member
951 struct vlv_wm_state optimal; /* inverted */ member
958 struct g4x_wm_state optimal; member
965 * safe intermediate watermarks to the optimal final
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Dintel_pm.c1375 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in g4x_compute_pipe_wm()
1456 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm() local
1461 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1465 *intermediate = *optimal; in g4x_compute_intermediate_wm()
1472 intermediate->cxsr = optimal->cxsr && active->cxsr && in g4x_compute_intermediate_wm()
1474 intermediate->hpll_en = optimal->hpll_en && active->hpll_en && in g4x_compute_intermediate_wm()
1476 intermediate->fbc_en = optimal->fbc_en && active->fbc_en; in g4x_compute_intermediate_wm()
1480 max(optimal->wm.plane[plane_id], in g4x_compute_intermediate_wm()
1487 intermediate->sr.plane = max(optimal in g4x_compute_intermediate_wm()
2099 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal; vlv_compute_intermediate_wm() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h733 struct intel_pipe_wm optimal; member
738 struct skl_pipe_wm optimal; member
749 /* optimal watermarks (inverted) */
750 struct vlv_wm_state optimal; member
760 /* optimal watermarks */
761 struct g4x_wm_state optimal; member
768 * safe intermediate watermarks to the optimal final
H A Dintel_display.c872 * Check if the calculated PLL configuration is more optimal compared to the
2292 * something and try to run the system in a "less than optimal" in intel_pin_and_fence_fb_obj()
6623 * optimal watermarks. For gen9+ platforms, the values we program here in intel_pre_plane_update()
14104 sw_wm = &new_crtc_state->wm.skl.optimal; in verify_wm_state()
15650 * optimal watermarks on platforms that need two-step watermark in intel_atomic_commit_tail()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx9.asm910 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
H A Dcwsr_trap_handler_gfx8.asm665 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx9.asm915 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
H A Dcwsr_trap_handler_gfx8.asm666 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time

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