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Searched refs:opp_id (Results 1 - 25 of 58) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c149 unsigned int opp_id; in mpc1_is_mpcc_idle() local
153 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
155 if (top_sel == 0xf && opp_id == 0xf && idle) in mpc1_is_mpcc_idle()
237 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
240 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id); in mpc1_insert_plane()
246 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); in mpc1_insert_plane()
302 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); in mpc1_remove_mpcc()
306 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); in mpc1_remove_mpcc()
375 int opp_id; in mpc1_mpc_init() local
387 for (opp_id in mpc1_mpc_init()
396 int opp_id; mpc1_mpc_init_single_inst() local
417 unsigned int opp_id; mpc1_init_mpcc_list_from_hw() local
476 mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock) mpc1_cursor_lock() argument
483 mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id) mpc1_get_mpc_out_mux() argument
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H A Ddcn10_mpc.h201 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
203 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c143 unsigned int opp_id; in mpc1_is_mpcc_idle() local
147 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
149 if (top_sel == 0xf && opp_id == 0xf && idle) in mpc1_is_mpcc_idle()
231 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
234 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id); in mpc1_insert_plane()
240 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); in mpc1_insert_plane()
296 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); in mpc1_remove_mpcc()
300 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); in mpc1_remove_mpcc()
369 int opp_id; in mpc1_mpc_init() local
381 for (opp_id in mpc1_mpc_init()
390 int opp_id; mpc1_mpc_init_single_inst() local
411 unsigned int opp_id; mpc1_init_mpcc_list_from_hw() local
470 mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock) mpc1_cursor_lock() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.c43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc31_set_odm_combine() argument
61 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc31_set_odm_combine()
63 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc31_set_odm_combine()
76 OPTC_SEG0_SRC_SEL, opp_id[0], in optc31_set_odm_combine()
77 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc31_set_odm_combine()
81 OPTC_SEG0_SRC_SEL, opp_id[0], in optc31_set_odm_combine()
82 OPTC_SEG1_SRC_SEL, opp_id[1], in optc31_set_odm_combine()
83 OPTC_SEG2_SRC_SEL, opp_id[ in optc31_set_odm_combine()
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H A Ddcn31_hubp.c109 hubp2->base.opp_id = OPP_ID_INVALID; in hubp31_construct()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.c50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc314_set_odm_combine() argument
74 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc314_set_odm_combine()
76 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc314_set_odm_combine()
87 OPTC_SEG0_SRC_SEL, opp_id[0], in optc314_set_odm_combine()
88 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc314_set_odm_combine()
92 OPTC_SEG0_SRC_SEL, opp_id[0], in optc314_set_odm_combine()
93 OPTC_SEG1_SRC_SEL, opp_id[1], in optc314_set_odm_combine()
94 OPTC_SEG2_SRC_SEL, opp_id[ in optc314_set_odm_combine()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_optc.c45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc32_set_odm_combine() argument
69 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2); in optc32_set_odm_combine()
71 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc32_set_odm_combine()
82 OPTC_SEG0_SRC_SEL, opp_id[0], in optc32_set_odm_combine()
83 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc32_set_odm_combine()
87 OPTC_SEG0_SRC_SEL, opp_id[0], in optc32_set_odm_combine()
88 OPTC_SEG1_SRC_SEL, opp_id[1], in optc32_set_odm_combine()
89 OPTC_SEG2_SRC_SEL, opp_id[ in optc32_set_odm_combine()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h168 * @opp_id: the OPP instance that owns this MPC tree
173 int opp_id; /* The OPP instance that owns this MPC tree */ member
187 uint32_t opp_id; member
291 * [in] opp_id - The OPP to lock cursor updates on
298 int opp_id,
361 int opp_id,
366 int opp_id,
370 int opp_id,
375 int opp_id,
402 int opp_id,
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.c205 static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument
230 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc3_set_odm_combine()
235 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2); in optc3_set_odm_combine()
245 OPTC_SEG0_SRC_SEL, opp_id[0], in optc3_set_odm_combine()
246 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc3_set_odm_combine()
250 OPTC_SEG0_SRC_SEL, opp_id[ in optc3_set_odm_combine()
[all...]
H A Ddcn30_mpc.c85 int opp_id, in mpc3_set_out_rate_control()
92 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
97 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
367 int opp_id, in mpc3_set_denorm()
400 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc3_set_denorm()
406 int opp_id, in mpc3_set_denorm_clamp()
412 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc3_set_denorm_clamp()
415 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc3_set_denorm_clamp()
418 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc3_set_denorm_clamp()
1204 int opp_id, in mpc3_set_output_csc()
83 mpc3_set_out_rate_control( struct mpc *mpc, int opp_id, bool enable, bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control) mpc3_set_out_rate_control() argument
365 mpc3_set_denorm( struct mpc *mpc, int opp_id, enum dc_color_depth output_depth) mpc3_set_denorm() argument
404 mpc3_set_denorm_clamp( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp) mpc3_set_denorm_clamp() argument
1202 mpc3_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) mpc3_set_output_csc() argument
1241 mpc3_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) mpc3_set_ocsc_default() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.c218 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument
243 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc3_set_odm_combine()
248 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2); in optc3_set_odm_combine()
258 OPTC_SEG0_SRC_SEL, opp_id[0], in optc3_set_odm_combine()
259 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc3_set_odm_combine()
263 OPTC_SEG0_SRC_SEL, opp_id[ in optc3_set_odm_combine()
[all...]
H A Ddcn30_mpc.c85 int opp_id, in mpc3_set_out_rate_control()
92 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
97 REG_UPDATE_2(MUX[opp_id], in mpc3_set_out_rate_control()
380 int opp_id, in mpc3_set_denorm()
413 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc3_set_denorm()
419 int opp_id, in mpc3_set_denorm_clamp()
425 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc3_set_denorm_clamp()
428 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc3_set_denorm_clamp()
431 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc3_set_denorm_clamp()
1236 int opp_id, in mpc3_set_output_csc()
83 mpc3_set_out_rate_control( struct mpc *mpc, int opp_id, bool enable, bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control) mpc3_set_out_rate_control() argument
378 mpc3_set_denorm( struct mpc *mpc, int opp_id, enum dc_color_depth output_depth) mpc3_set_denorm() argument
417 mpc3_set_denorm_clamp( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp) mpc3_set_denorm_clamp() argument
1234 mpc3_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) mpc3_set_output_csc() argument
1273 mpc3_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) mpc3_set_ocsc_default() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h135 int opp_id; /* The OPP instance that owns this MPC tree */ member
149 uint32_t opp_id; member
240 * [in] opp_id - The OPP to lock cursor updates on
247 int opp_id,
307 int opp_id,
312 int opp_id,
316 int opp_id,
321 int opp_id,
349 int opp_id,
H A Dhubp.h64 int opp_id; member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c76 int opp_id, in mpc2_set_denorm()
108 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc2_set_denorm()
114 int opp_id, in mpc2_set_denorm_clamp()
119 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc2_set_denorm_clamp()
122 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc2_set_denorm_clamp()
125 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc2_set_denorm_clamp()
134 int opp_id, in mpc2_set_output_csc()
143 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
171 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc()
172 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc()
74 mpc2_set_denorm( struct mpc *mpc, int opp_id, enum dc_color_depth output_depth) mpc2_set_denorm() argument
112 mpc2_set_denorm_clamp( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp) mpc2_set_denorm_clamp() argument
132 mpc2_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) mpc2_set_output_csc() argument
186 mpc2_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) mpc2_set_ocsc_default() argument
[all...]
H A Ddcn20_optc.c235 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
258 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc2_set_odm_combine()
266 OPTC_SEG0_SRC_SEL, opp_id[0], in optc2_set_odm_combine()
267 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc2_set_odm_combine()
H A Ddcn20_mpc.h284 int opp_id,
289 int opp_id,
294 int opp_id,
300 int opp_id,
H A Ddcn20_hwseq.h51 int opp_id);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c75 int opp_id, in mpc2_set_denorm()
107 REG_UPDATE(DENORM_CONTROL[opp_id], in mpc2_set_denorm()
113 int opp_id, in mpc2_set_denorm_clamp()
118 REG_UPDATE_2(DENORM_CONTROL[opp_id], in mpc2_set_denorm_clamp()
121 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], in mpc2_set_denorm_clamp()
124 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], in mpc2_set_denorm_clamp()
133 int opp_id, in mpc2_set_output_csc()
142 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
170 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc()
171 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc()
73 mpc2_set_denorm( struct mpc *mpc, int opp_id, enum dc_color_depth output_depth) mpc2_set_denorm() argument
111 mpc2_set_denorm_clamp( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp) mpc2_set_denorm_clamp() argument
131 mpc2_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) mpc2_set_output_csc() argument
185 mpc2_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) mpc2_set_ocsc_default() argument
[all...]
H A Ddcn20_optc.c188 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
211 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); in optc2_set_odm_combine()
219 OPTC_SEG0_SRC_SEL, opp_id[0], in optc2_set_odm_combine()
220 OPTC_SEG1_SRC_SEL, opp_id[1]); in optc2_set_odm_combine()
H A Ddcn20_mpc.h284 int opp_id,
289 int opp_id,
294 int opp_id,
300 int opp_id,
H A Ddcn20_hwseq.h51 int opp_id);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c44 int opp_id, in mpc201_set_out_rate_control()
51 REG_UPDATE_2(MUX[opp_id], in mpc201_set_out_rate_control()
56 REG_UPDATE_3(MUX[opp_id], in mpc201_set_out_rate_control()
42 mpc201_set_out_rate_control( struct mpc *mpc, int opp_id, bool enable, bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control) mpc201_set_out_rate_control() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c575 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst; in hwss_build_fast_sequence()
582 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst; in hwss_build_fast_sequence()
767 int opp_id = params->set_output_csc_params.opp_id; in hwss_set_output_csc() local
773 opp_id, in hwss_set_output_csc()
781 int opp_id = params->set_ocsc_default_params.opp_id; in hwss_set_ocsc_default() local
787 opp_id, in hwss_set_ocsc_default()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/
H A Dhw_sequencer.h125 int opp_id; member
132 int opp_id; member
292 uint16_t *matrix, int opp_id);

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