| /kernel/linux/linux-5.10/drivers/gpu/drm/qxl/ |
| H A D | qxl_drv.c | 61 MODULE_PARM_DESC(num_heads, "Number of virtual crtcs to expose (default 4)");
62 module_param_named(num_heads, qxl_num_crtc, int, 0400);
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/qxl/ |
| H A D | qxl_drv.c | 65 MODULE_PARM_DESC(num_heads, "Number of virtual crtcs to expose (default 4)");
66 module_param_named(num_heads, qxl_num_crtc, int, 0400);
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| H A D | hub.c | 766 unsigned int i = hub->num_heads; in tegra_display_hub_runtime_suspend()
810 for (i = 0; i < hub->num_heads; i++) { in tegra_display_hub_runtime_resume()
906 hub->num_heads = of_get_child_count(pdev->dev.of_node); in tegra_display_hub_probe()
908 hub->clk_heads = devm_kcalloc(&pdev->dev, hub->num_heads, sizeof(clk), in tegra_display_hub_probe()
913 for (i = 0; i < hub->num_heads; i++) { in tegra_display_hub_probe()
|
| H A D | hub.h | 48 unsigned int num_heads; member
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/tegra/ |
| H A D | hub.h | 48 unsigned int num_heads; member
|
| H A D | hub.c | 973 unsigned int i = hub->num_heads; in tegra_display_hub_runtime_suspend()
1017 for (i = 0; i < hub->num_heads; i++) { in tegra_display_hub_runtime_resume()
1120 hub->num_heads = of_get_child_count(pdev->dev.of_node); in tegra_display_hub_probe()
1122 hub->clk_heads = devm_kcalloc(&pdev->dev, hub->num_heads, sizeof(clk), in tegra_display_hub_probe()
1127 for (i = 0; i < hub->num_heads; i++) { in tegra_display_hub_probe()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | dce_v6_0.c | 503 u32 num_heads; /* number of active crtcs */ member
696 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v6_0_latency_watermark()
697 (wm->num_heads * cursor_line_pair_return_time); in dce_v6_0_latency_watermark()
703 if (wm->num_heads == 0) in dce_v6_0_latency_watermark()
717 b.full = dfixed_const(wm->num_heads); in dce_v6_0_latency_watermark()
752 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display()
772 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_available_bandwidth()
819 * @num_heads: number of display controllers in use
826 u32 lb_size, u32 num_heads) in dce_v6_0_program_watermarks()
840 if (amdgpu_crtc->base.enabled && num_heads in dce_v6_0_program_watermarks()
824 dce_v6_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) dce_v6_0_program_watermarks() argument
1062 u32 num_heads = 0, lb_size; dce_v6_0_bandwidth_update() local
[all...] |
| H A D | dce_v11_0.c | 731 u32 num_heads; /* number of active crtcs */ member
924 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v11_0_latency_watermark()
925 (wm->num_heads * cursor_line_pair_return_time); in dce_v11_0_latency_watermark()
931 if (wm->num_heads == 0) in dce_v11_0_latency_watermark()
945 b.full = dfixed_const(wm->num_heads); in dce_v11_0_latency_watermark()
980 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display()
1000 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_available_bandwidth()
1047 * @num_heads: number of display controllers in use
1054 u32 lb_size, u32 num_heads) in dce_v11_0_program_watermarks()
1063 if (amdgpu_crtc->base.enabled && num_heads in dce_v11_0_program_watermarks()
1052 dce_v11_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) dce_v11_0_program_watermarks() argument
1187 u32 num_heads = 0, lb_size; dce_v11_0_bandwidth_update() local
[all...] |
| H A D | dce_v8_0.c | 640 u32 num_heads; /* number of active crtcs */ member
833 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v8_0_latency_watermark()
834 (wm->num_heads * cursor_line_pair_return_time); in dce_v8_0_latency_watermark()
840 if (wm->num_heads == 0) in dce_v8_0_latency_watermark()
854 b.full = dfixed_const(wm->num_heads); in dce_v8_0_latency_watermark()
889 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display()
909 (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) in dce_v8_0_average_bandwidth_vs_available_bandwidth()
956 * @num_heads: number of display controllers in use
963 u32 lb_size, u32 num_heads) in dce_v8_0_program_watermarks()
972 if (amdgpu_crtc->base.enabled && num_heads in dce_v8_0_program_watermarks()
961 dce_v8_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) dce_v8_0_program_watermarks() argument
1098 u32 num_heads = 0, lb_size; dce_v8_0_bandwidth_update() local
[all...] |
| H A D | dce_v10_0.c | 705 u32 num_heads; /* number of active crtcs */ member
898 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v10_0_latency_watermark()
899 (wm->num_heads * cursor_line_pair_return_time); in dce_v10_0_latency_watermark()
905 if (wm->num_heads == 0) in dce_v10_0_latency_watermark()
919 b.full = dfixed_const(wm->num_heads); in dce_v10_0_latency_watermark()
954 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display()
974 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_available_bandwidth()
1021 * @num_heads: number of display controllers in use
1028 u32 lb_size, u32 num_heads) in dce_v10_0_program_watermarks()
1037 if (amdgpu_crtc->base.enabled && num_heads in dce_v10_0_program_watermarks()
1026 dce_v10_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) dce_v10_0_program_watermarks() argument
1161 u32 num_heads = 0, lb_size; dce_v10_0_bandwidth_update() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | dce_v6_0.c | 506 u32 num_heads; /* number of active crtcs */ member
699 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v6_0_latency_watermark()
700 (wm->num_heads * cursor_line_pair_return_time); in dce_v6_0_latency_watermark()
706 if (wm->num_heads == 0) in dce_v6_0_latency_watermark()
720 b.full = dfixed_const(wm->num_heads); in dce_v6_0_latency_watermark()
755 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display()
775 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_available_bandwidth()
822 * @num_heads: number of display controllers in use
829 u32 lb_size, u32 num_heads) in dce_v6_0_program_watermarks()
843 if (amdgpu_crtc->base.enabled && num_heads in dce_v6_0_program_watermarks()
827 dce_v6_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) dce_v6_0_program_watermarks() argument
1064 u32 num_heads = 0, lb_size; dce_v6_0_bandwidth_update() local
[all...] |
| H A D | dce_v8_0.c | 641 u32 num_heads; /* number of active crtcs */ member
834 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v8_0_latency_watermark()
835 (wm->num_heads * cursor_line_pair_return_time); in dce_v8_0_latency_watermark()
841 if (wm->num_heads == 0) in dce_v8_0_latency_watermark()
855 b.full = dfixed_const(wm->num_heads); in dce_v8_0_latency_watermark()
890 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display()
910 (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) in dce_v8_0_average_bandwidth_vs_available_bandwidth()
957 * @num_heads: number of display controllers in use
964 u32 lb_size, u32 num_heads) in dce_v8_0_program_watermarks()
973 if (amdgpu_crtc->base.enabled && num_heads in dce_v8_0_program_watermarks()
962 dce_v8_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) dce_v8_0_program_watermarks() argument
1099 u32 num_heads = 0, lb_size; dce_v8_0_bandwidth_update() local
[all...] |
| H A D | dce_v11_0.c | 734 u32 num_heads; /* number of active crtcs */ member
927 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v11_0_latency_watermark()
928 (wm->num_heads * cursor_line_pair_return_time); in dce_v11_0_latency_watermark()
934 if (wm->num_heads == 0) in dce_v11_0_latency_watermark()
948 b.full = dfixed_const(wm->num_heads); in dce_v11_0_latency_watermark()
983 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display()
1003 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_available_bandwidth()
1050 * @num_heads: number of display controllers in use
1057 u32 lb_size, u32 num_heads) in dce_v11_0_program_watermarks()
1066 if (amdgpu_crtc->base.enabled && num_heads in dce_v11_0_program_watermarks()
1055 dce_v11_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) dce_v11_0_program_watermarks() argument
1190 u32 num_heads = 0, lb_size; dce_v11_0_bandwidth_update() local
[all...] |
| H A D | dce_v10_0.c | 702 u32 num_heads; /* number of active crtcs */ member
895 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v10_0_latency_watermark()
896 (wm->num_heads * cursor_line_pair_return_time); in dce_v10_0_latency_watermark()
902 if (wm->num_heads == 0) in dce_v10_0_latency_watermark()
916 b.full = dfixed_const(wm->num_heads); in dce_v10_0_latency_watermark()
951 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display()
971 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_available_bandwidth()
1018 * @num_heads: number of display controllers in use
1025 u32 lb_size, u32 num_heads) in dce_v10_0_program_watermarks()
1034 if (amdgpu_crtc->base.enabled && num_heads in dce_v10_0_program_watermarks()
1023 dce_v10_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) dce_v10_0_program_watermarks() argument
1158 u32 num_heads = 0, lb_size; dce_v10_0_bandwidth_update() local
[all...] |
| /kernel/linux/linux-5.10/fs/btrfs/ |
| H A D | delayed-ref.h | 154 unsigned long num_heads; member
|
| H A D | delayed-ref.c | 583 delayed_refs->num_heads--; in btrfs_delete_ref_head()
861 delayed_refs->num_heads++; in add_delayed_ref_head()
|
| /kernel/linux/linux-6.6/fs/btrfs/ |
| H A D | delayed-ref.h | 161 unsigned long num_heads; member
|
| H A D | delayed-ref.c | 575 delayed_refs->num_heads--; in btrfs_delete_ref_head()
828 delayed_refs->num_heads++; in add_delayed_ref_head()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | evergreen.c | 1941 u32 num_heads; /* number of active crtcs */ member
2069 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in evergreen_latency_watermark()
2070 (wm->num_heads * cursor_line_pair_return_time); in evergreen_latency_watermark()
2075 if (wm->num_heads == 0) in evergreen_latency_watermark()
2089 b.full = dfixed_const(wm->num_heads); in evergreen_latency_watermark()
2111 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) in evergreen_average_bandwidth_vs_dram_bandwidth_for_display()
2120 (evergreen_available_bandwidth(wm) / wm->num_heads)) in evergreen_average_bandwidth_vs_available_bandwidth()
2154 u32 lb_size, u32 num_heads) in evergreen_program_watermarks()
2169 if (radeon_crtc->base.enabled && num_heads && mode) { in evergreen_program_watermarks()
2204 wm_high.num_heads in evergreen_program_watermarks()
2152 evergreen_program_watermarks(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc, u32 lb_size, u32 num_heads) evergreen_program_watermarks() argument
2325 u32 num_heads = 0, lb_size; evergreen_bandwidth_update() local
[all...] |
| H A D | si.c | 2067 u32 num_heads; /* number of active crtcs */ member
2212 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce6_latency_watermark()
2213 (wm->num_heads * cursor_line_pair_return_time); in dce6_latency_watermark()
2219 if (wm->num_heads == 0) in dce6_latency_watermark()
2233 b.full = dfixed_const(wm->num_heads); in dce6_latency_watermark()
2257 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_dram_bandwidth_for_display()
2266 (dce6_available_bandwidth(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_available_bandwidth()
2300 u32 lb_size, u32 num_heads) in dce6_program_watermarks()
2314 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
2353 wm_high.num_heads in dce6_program_watermarks()
2298 dce6_program_watermarks(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc, u32 lb_size, u32 num_heads) dce6_program_watermarks() argument
2468 u32 num_heads = 0, lb_size; dce6_bandwidth_update() local
[all...] |
| H A D | cik.c | 8926 u32 num_heads; /* number of active crtcs */ member
9119 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce8_latency_watermark()
9120 (wm->num_heads * cursor_line_pair_return_time); in dce8_latency_watermark()
9126 if (wm->num_heads == 0) in dce8_latency_watermark()
9140 b.full = dfixed_const(wm->num_heads); in dce8_latency_watermark()
9175 (dce8_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce8_average_bandwidth_vs_dram_bandwidth_for_display()
9195 (dce8_available_bandwidth(wm) / wm->num_heads)) in dce8_average_bandwidth_vs_available_bandwidth()
9242 * @num_heads: number of display controllers in use
9249 u32 lb_size, u32 num_heads) in dce8_program_watermarks()
9258 if (radeon_crtc->base.enabled && num_heads in dce8_program_watermarks()
9247 dce8_program_watermarks(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc, u32 lb_size, u32 num_heads) dce8_program_watermarks() argument
9386 u32 num_heads = 0, lb_size; dce8_bandwidth_update() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | si.c | 2062 u32 num_heads; /* number of active crtcs */ member
2207 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce6_latency_watermark()
2208 (wm->num_heads * cursor_line_pair_return_time); in dce6_latency_watermark()
2214 if (wm->num_heads == 0) in dce6_latency_watermark()
2228 b.full = dfixed_const(wm->num_heads); in dce6_latency_watermark()
2252 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_dram_bandwidth_for_display()
2261 (dce6_available_bandwidth(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_available_bandwidth()
2295 u32 lb_size, u32 num_heads) in dce6_program_watermarks()
2309 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
2348 wm_high.num_heads in dce6_program_watermarks()
2293 dce6_program_watermarks(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc, u32 lb_size, u32 num_heads) dce6_program_watermarks() argument
2463 u32 num_heads = 0, lb_size; dce6_bandwidth_update() local
[all...] |
| H A D | evergreen.c | 1943 u32 num_heads; /* number of active crtcs */ member
2071 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in evergreen_latency_watermark()
2072 (wm->num_heads * cursor_line_pair_return_time); in evergreen_latency_watermark()
2077 if (wm->num_heads == 0) in evergreen_latency_watermark()
2091 b.full = dfixed_const(wm->num_heads); in evergreen_latency_watermark()
2113 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) in evergreen_average_bandwidth_vs_dram_bandwidth_for_display()
2122 (evergreen_available_bandwidth(wm) / wm->num_heads)) in evergreen_average_bandwidth_vs_available_bandwidth()
2156 u32 lb_size, u32 num_heads) in evergreen_program_watermarks()
2171 if (radeon_crtc->base.enabled && num_heads && mode) { in evergreen_program_watermarks()
2206 wm_high.num_heads in evergreen_program_watermarks()
2154 evergreen_program_watermarks(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc, u32 lb_size, u32 num_heads) evergreen_program_watermarks() argument
2327 u32 num_heads = 0, lb_size; evergreen_bandwidth_update() local
[all...] |
| H A D | cik.c | 8908 u32 num_heads; /* number of active crtcs */ member
9101 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce8_latency_watermark()
9102 (wm->num_heads * cursor_line_pair_return_time); in dce8_latency_watermark()
9108 if (wm->num_heads == 0) in dce8_latency_watermark()
9122 b.full = dfixed_const(wm->num_heads); in dce8_latency_watermark()
9157 (dce8_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce8_average_bandwidth_vs_dram_bandwidth_for_display()
9177 (dce8_available_bandwidth(wm) / wm->num_heads)) in dce8_average_bandwidth_vs_available_bandwidth()
9224 * @num_heads: number of display controllers in use
9231 u32 lb_size, u32 num_heads) in dce8_program_watermarks()
9240 if (radeon_crtc->base.enabled && num_heads in dce8_program_watermarks()
9229 dce8_program_watermarks(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc, u32 lb_size, u32 num_heads) dce8_program_watermarks() argument
9368 u32 num_heads = 0, lb_size; dce8_bandwidth_update() local
[all...] |