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Searched refs:num_dcfclk_sta_targets (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c206 unsigned int num_dcfclk_sta_targets = 4; in dcn302_fpu_update_bw_bounding_box() local
242 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box()
244 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
245 num_dcfclk_sta_targets++; in dcn302_fpu_update_bw_bounding_box()
246 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box()
248 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn302_fpu_update_bw_bounding_box()
255 num_dcfclk_sta_targets = i + 1; in dcn302_fpu_update_bw_bounding_box()
269 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn302_fpu_update_bw_bounding_box()
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
283 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn302_fpu_update_bw_bounding_box()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c202 unsigned int num_dcfclk_sta_targets = 4; in dcn303_fpu_update_bw_bounding_box() local
238 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box()
239 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
240 num_dcfclk_sta_targets++; in dcn303_fpu_update_bw_bounding_box()
241 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box()
242 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn303_fpu_update_bw_bounding_box()
249 num_dcfclk_sta_targets = i + 1; in dcn303_fpu_update_bw_bounding_box()
263 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn303_fpu_update_bw_bounding_box()
276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
277 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn303_fpu_update_bw_bounding_box()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c704 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn321_update_bw_bounding_box_fpu() local
726 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu()
728 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu()
729 num_dcfclk_sta_targets++; in dcn321_update_bw_bounding_box_fpu()
730 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu()
732 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn321_update_bw_bounding_box_fpu()
739 num_dcfclk_sta_targets = i + 1; in dcn321_update_bw_bounding_box_fpu()
754 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn321_update_bw_bounding_box_fpu()
767 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
768 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn321_update_bw_bounding_box_fpu()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c2100 unsigned int num_dcfclk_sta_targets = 4; in dcn30_update_bw_bounding_box() local
2131 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box()
2133 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz; in dcn30_update_bw_bounding_box()
2134 num_dcfclk_sta_targets++; in dcn30_update_bw_bounding_box()
2135 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box()
2137 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn30_update_bw_bounding_box()
2144 num_dcfclk_sta_targets = i + 1; in dcn30_update_bw_bounding_box()
2161 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn30_update_bw_bounding_box()
2174 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2175 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn30_update_bw_bounding_box()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c2470 unsigned int num_dcfclk_sta_targets = 4; in dcn30_update_bw_bounding_box() local
2505 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box()
2507 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn30_update_bw_bounding_box()
2508 num_dcfclk_sta_targets++; in dcn30_update_bw_bounding_box()
2509 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box()
2511 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn30_update_bw_bounding_box()
2518 num_dcfclk_sta_targets = i + 1; in dcn30_update_bw_bounding_box()
2535 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn30_update_bw_bounding_box()
2548 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2549 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn30_update_bw_bounding_box()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c2795 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn32_update_bw_bounding_box_fpu() local
2822 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu()
2824 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn32_update_bw_bounding_box_fpu()
2825 num_dcfclk_sta_targets++; in dcn32_update_bw_bounding_box_fpu()
2826 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu()
2828 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn32_update_bw_bounding_box_fpu()
2835 num_dcfclk_sta_targets = i + 1; in dcn32_update_bw_bounding_box_fpu()
2850 for (i = 0; i < num_dcfclk_sta_targets; i++) { in dcn32_update_bw_bounding_box_fpu()
2863 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()
2864 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn32_update_bw_bounding_box_fpu()
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