/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
H A D | radeon_object.c | 618 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local 622 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; in radeon_bo_set_tiling_flags() 645 switch (mtaspect) { in radeon_bo_set_tiling_flags()
|
H A D | evergreen_cs.c | 1182 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local 1185 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg() 1191 DB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg() 1446 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local 1449 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg() 1455 CB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg() 1474 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local 1477 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg() 1483 CB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg() 2363 unsigned bankw, bankh, mtaspect, tile_spli in evergreen_packet3_check() local [all...] |
H A D | atombios_crtc.c | 1146 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local 1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base() 1334 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); in dce4_crtc_do_set_base()
|
H A D | evergreen.c | 1111 unsigned *bankh, unsigned *mtaspect, in evergreen_tiling_fields() 1116 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; in evergreen_tiling_fields() 1132 switch (*mtaspect) { in evergreen_tiling_fields() 1134 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break; in evergreen_tiling_fields() 1135 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break; in evergreen_tiling_fields() 1136 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break; in evergreen_tiling_fields() 1137 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break; in evergreen_tiling_fields() 1110 evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, unsigned *bankh, unsigned *mtaspect, unsigned *tile_split) evergreen_tiling_fields() argument
|
H A D | radeon.h | 357 unsigned *bankh, unsigned *mtaspect,
|
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
H A D | evergreen_cs.c | 1183 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local 1186 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg() 1192 DB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg() 1447 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local 1450 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg() 1456 CB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg() 1475 unsigned bankw, bankh, mtaspect, tile_split; in evergreen_cs_handle_reg() local 1478 &bankw, &bankh, &mtaspect, in evergreen_cs_handle_reg() 1484 CB_MACRO_TILE_ASPECT(mtaspect); in evergreen_cs_handle_reg() 2364 unsigned bankw, bankh, mtaspect, tile_spli in evergreen_packet3_check() local [all...] |
H A D | radeon_object.c | 682 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local 686 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; in radeon_bo_set_tiling_flags() 709 switch (mtaspect) { in radeon_bo_set_tiling_flags()
|
H A D | atombios_crtc.c | 1155 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local 1276 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base() 1344 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); in dce4_crtc_do_set_base()
|
H A D | evergreen.c | 1115 unsigned *bankh, unsigned *mtaspect, in evergreen_tiling_fields() 1120 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; in evergreen_tiling_fields() 1136 switch (*mtaspect) { in evergreen_tiling_fields() 1138 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break; in evergreen_tiling_fields() 1139 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break; in evergreen_tiling_fields() 1140 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break; in evergreen_tiling_fields() 1141 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break; in evergreen_tiling_fields() 1114 evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, unsigned *bankh, unsigned *mtaspect, unsigned *tile_split) evergreen_tiling_fields() argument
|
H A D | radeon.h | 357 unsigned *bankh, unsigned *mtaspect,
|
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_plane.c | 185 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; in fill_gfx8_tiling_info_from_flags() local 189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in fill_gfx8_tiling_info_from_flags() 200 tiling_info->gfx8.tile_aspect = mtaspect; in fill_gfx8_tiling_info_from_flags()
|
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
H A D | dce_v11_0.c | 2031 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v11_0_crtc_do_set_base() local 2035 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base() 2047 mtaspect); in dce_v11_0_crtc_do_set_base()
|
H A D | dce_v8_0.c | 1910 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local 1914 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base() 1923 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); in dce_v8_0_crtc_do_set_base()
|
H A D | dce_v10_0.c | 1989 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local 1993 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base() 2005 mtaspect); in dce_v10_0_crtc_do_set_base()
|
H A D | dce_v6_0.c | 1938 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local 1942 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base() 1951 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); in dce_v6_0_crtc_do_set_base()
|
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
H A D | dce_v8_0.c | 1908 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v8_0_crtc_do_set_base() local 1912 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base() 1921 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); in dce_v8_0_crtc_do_set_base()
|
H A D | dce_v11_0.c | 2033 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v11_0_crtc_do_set_base() local 2037 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base() 2049 mtaspect); in dce_v11_0_crtc_do_set_base()
|
H A D | dce_v10_0.c | 1983 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v10_0_crtc_do_set_base() local 1987 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base() 1999 mtaspect); in dce_v10_0_crtc_do_set_base()
|
H A D | dce_v6_0.c | 1939 unsigned bankw, bankh, mtaspect, tile_split, num_banks; in dce_v6_0_crtc_do_set_base() local 1943 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base() 1952 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); in dce_v6_0_crtc_do_set_base()
|
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 3978 unsigned int bankw, bankh, mtaspect, tile_split, num_banks; 3982 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 3993 tiling_info->gfx8.tile_aspect = mtaspect;
|