Searched refs:msix_ctrl (Results 1 - 5 of 5) sorted by relevance
| /kernel/linux/linux-6.6/drivers/pci/msi/ |
| H A D | msi.h | 33 * It does not affect the msi_desc::msix_ctrl cache either. Use with care!
45 desc->pci.msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT; in pci_msix_mask()
46 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl); in pci_msix_mask()
53 desc->pci.msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; in pci_msix_unmask()
54 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl); in pci_msix_unmask()
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| H A D | msi.c | 208 u32 ctrl = desc->pci.msix_ctrl; in pci_write_msg_msix()
603 desc->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); in msix_prepare_msi_desc()
863 pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl); in __pci_restore_msix_state()
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| /kernel/linux/linux-6.6/drivers/net/ethernet/huawei/hinic/ |
| H A D | hinic_hw_if.c | 43 u32 msix_ctrl, addr; in hinic_msix_attr_set() local
48 msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | in hinic_msix_attr_set()
56 hinic_hwif_write_reg(hwif, addr, msix_ctrl); in hinic_msix_attr_set()
69 u32 msix_ctrl, addr; in hinic_msix_attr_cnt_clear() local
74 msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER); in hinic_msix_attr_cnt_clear()
77 hinic_hwif_write_reg(hwif, addr, msix_ctrl); in hinic_msix_attr_cnt_clear()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/huawei/hinic/ |
| H A D | hinic_hw_if.c | 43 u32 msix_ctrl, addr; in hinic_msix_attr_set() local
48 msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | in hinic_msix_attr_set()
56 hinic_hwif_write_reg(hwif, addr, msix_ctrl); in hinic_msix_attr_set()
102 u32 msix_ctrl, addr; in hinic_msix_attr_cnt_clear() local
107 msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER); in hinic_msix_attr_cnt_clear()
110 hinic_hwif_write_reg(hwif, addr, msix_ctrl); in hinic_msix_attr_cnt_clear()
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| /kernel/linux/linux-6.6/include/linux/ |
| H A D | msi.h | 103 * @msix_ctrl: [PCI MSI-X] MSI-X cached per vector control bits
116 u32 msix_ctrl; member
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