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Searched refs:mpcc (Results 1 - 22 of 22) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c62 static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc201_init_mpcc() argument
64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
65 mpcc->dpp_id = 0xf; in mpc201_init_mpcc()
66 mpcc->mpcc_bot = NULL; in mpc201_init_mpcc()
67 mpcc->blnd_cfg.overlap_only = false; in mpc201_init_mpcc()
68 mpcc->blnd_cfg.global_alpha = 0xff; in mpc201_init_mpcc()
69 mpcc->blnd_cfg.global_gain = 0xff; in mpc201_init_mpcc()
70 mpcc->blnd_cfg.background_color_bpc = 4; in mpc201_init_mpcc()
71 mpcc in mpc201_init_mpcc()
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H A Ddcn201_hwseq.c379 struct mpcc *mpcc_to_remove = NULL; in dcn201_plane_atomic_disconnect()
424 struct mpcc *new_mpcc; in dcn201_update_mpcc()
425 struct mpcc *remove_mpcc = NULL; in dcn201_update_mpcc()
473 * we do mpcc_remove but the mpcc cannot go to idle in dcn201_update_mpcc()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h120 struct mpcc { struct
123 struct mpcc *mpcc_bot; /* pointer to bottom layer MPCC. NULL when not connected */
136 struct mpcc *opp_list; /* The top MPCC layer of the MPC tree that outputs to OPP endpoint */
143 struct mpcc mpcc_array[MAX_MPCC];
180 * Return: struct mpcc* - MPCC that was added.
182 struct mpcc* (*insert_plane)(
187 struct mpcc *insert_above_mpcc,
197 * [in/out] mpcc - MPCC to be removed from tree.
204 struct mpcc *mpcc);
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H A Dopp.h201 int mpcc[MAX_PIPES]; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h146 * struct mpcc - MPCC connection and blending configuration for a single MPCC instance.
156 struct mpcc { struct
159 struct mpcc *mpcc_bot; /* pointer to bottom layer MPCC. NULL when not connected */
174 struct mpcc *opp_list; /* The top MPCC layer of the MPC tree that outputs to OPP endpoint */
181 struct mpcc mpcc_array[MAX_MPCC];
223 * Return: struct mpcc* - MPCC that was added.
225 struct mpcc* (*insert_plane)(
230 struct mpcc *insert_above_mpcc,
242 * [in/out] mpcc - MPCC to be removed from tree.
249 struct mpcc *mpc
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H A Dopp.h201 int mpcc[MAX_PIPES]; member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_set_bg_color()
48 /* find bottommost mpcc. */ in mpc1_set_bg_color()
75 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_update_blending() local
85 mpcc->blnd_cfg = *blnd_cfg; in mpc1_update_blending()
113 struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) in mpc1_get_mpcc()
121 struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) in mpc1_get_mpcc_for_dpp()
123 struct mpcc *tmp_mpcc = tree->opp_list; in mpc1_get_mpcc_for_dpp()
187 * Return: struct mpcc* - MPCC that was added.
189 struct mpcc *mpc1_insert_plan
346 mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) mpc1_init_mpcc() argument
415 struct mpcc *mpcc; mpc1_init_mpcc_list_from_hw() local
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H A Ddcn10_mpc.h141 struct mpcc *mpc1_insert_plane(
146 struct mpcc *insert_above_mpcc,
153 struct mpcc *mpcc);
188 struct mpcc *mpc1_get_mpcc(
192 struct mpcc *mpc1_get_mpcc_for_dpp(
H A Ddcn10_hw_sequencer.c1054 struct mpcc *mpcc_to_remove = NULL; in dcn10_plane_atomic_disconnect()
1193 /* num_opp will be equal to number of mpcc */ in dcn10_init_pipes()
2374 struct mpcc *new_mpcc; in dcn10_update_mpcc()
2419 * we do mpcc_remove but the mpcc cannot go to idle in dcn10_update_mpcc()
2816 /* Disconnect mpcc here only if losing pipe split*/ in dcn10_disconnect_pipes()
2839 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); in dcn10_disconnect_pipes()
2971 /* Disconnect unused mpcc */ in dcn10_apply_ctx_for_surface()
2985 DC_LOG_DC("Reset mpcc for pipe %d\n", in dcn10_apply_ctx_for_surface()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_set_bg_color()
50 /* find bottommost mpcc. */ in mpc1_set_bg_color()
82 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc1_update_blending() local
91 mpcc->blnd_cfg = *blnd_cfg; in mpc1_update_blending()
119 struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) in mpc1_get_mpcc()
127 struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id) in mpc1_get_mpcc_for_dpp()
129 struct mpcc *tmp_mpcc = tree->opp_list; in mpc1_get_mpcc_for_dpp()
193 * Return: struct mpcc* - MPCC that was added.
195 struct mpcc *mpc1_insert_plan
352 mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) mpc1_init_mpcc() argument
421 struct mpcc *mpcc; mpc1_init_mpcc_list_from_hw() local
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H A Ddcn10_mpc.h141 struct mpcc *mpc1_insert_plane(
146 struct mpcc *insert_above_mpcc,
153 struct mpcc *mpcc);
188 struct mpcc *mpc1_get_mpcc(
192 struct mpcc *mpc1_get_mpcc_for_dpp(
H A Ddcn10_hw_sequencer.c1188 struct mpcc *mpcc_to_remove = NULL; in dcn10_plane_atomic_disconnect()
1362 /* num_opp will be equal to number of mpcc */ in dcn10_init_pipes()
2607 struct mpcc *new_mpcc; in dcn10_update_mpcc()
2641 * we do mpcc_remove but the mpcc cannot go to idle in dcn10_update_mpcc()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c55 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc2_update_blending() local
71 mpcc->blnd_cfg = *blnd_cfg; in mpc2_update_blending()
513 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc2_init_mpcc() argument
515 mpcc->mpcc_id = mpcc_inst; in mpc2_init_mpcc()
516 mpcc->dpp_id = 0xf; in mpc2_init_mpcc()
517 mpcc->mpcc_bot = NULL; in mpc2_init_mpcc()
518 mpcc->blnd_cfg.overlap_only = false; in mpc2_init_mpcc()
519 mpcc in mpc2_init_mpcc()
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H A Ddcn20_hwseq.c1241 new_pipe->update_flags.bits.mpcc = 1; in dcn20_detect_pipe_changes()
1284 * Assume mpcc inst = pipe index, if not this code needs to be updated in dcn20_detect_pipe_changes()
1285 * since mpcc is what is affected by these. In fact all of our sequence in dcn20_detect_pipe_changes()
1287 * same index mpcc reset. in dcn20_detect_pipe_changes()
1295 * Detect mpcc blending changes, only dpp inst and opp matter here, in dcn20_detect_pipe_changes()
1301 new_pipe->update_flags.bits.mpcc = 1; in dcn20_detect_pipe_changes()
1427 if (pipe_ctx->update_flags.bits.mpcc in dcn20_update_dchubp_dpp()
1688 /* Disconnect mpcc */ in dcn20_program_front_end_for_ctx()
1693 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); in dcn20_program_front_end_for_ctx()
1697 * Program all updated pipes, order matters for mpcc setu in dcn20_program_front_end_for_ctx()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c55 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); in mpc2_update_blending() local
70 mpcc->blnd_cfg = *blnd_cfg; in mpc2_update_blending()
511 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc2_init_mpcc() argument
513 mpcc->mpcc_id = mpcc_inst; in mpc2_init_mpcc()
514 mpcc->dpp_id = 0xf; in mpc2_init_mpcc()
515 mpcc->mpcc_bot = NULL; in mpc2_init_mpcc()
516 mpcc->blnd_cfg.overlap_only = false; in mpc2_init_mpcc()
517 mpcc in mpc2_init_mpcc()
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H A Ddcn20_hwseq.c1341 new_pipe->update_flags.bits.mpcc = 1; in dcn20_detect_pipe_changes()
1405 * Assume mpcc inst = pipe index, if not this code needs to be updated in dcn20_detect_pipe_changes()
1406 * since mpcc is what is affected by these. In fact all of our sequence in dcn20_detect_pipe_changes()
1408 * same index mpcc reset. in dcn20_detect_pipe_changes()
1416 * Detect mpcc blending changes, only dpp inst and opp matter here, in dcn20_detect_pipe_changes()
1422 new_pipe->update_flags.bits.mpcc = 1; in dcn20_detect_pipe_changes()
1559 if (pipe_ctx->update_flags.bits.mpcc in dcn20_update_dchubp_dpp()
1870 /* Disconnect mpcc */ in dcn20_program_front_end_for_ctx()
1886 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); in dcn20_program_front_end_for_ctx()
1890 * Program all updated pipes, order matters for mpcc setu in dcn20_program_front_end_for_ctx()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c1009 static void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc3_init_mpcc() argument
1011 mpcc->mpcc_id = mpcc_inst; in mpc3_init_mpcc()
1012 mpcc->dpp_id = 0xf; in mpc3_init_mpcc()
1013 mpcc->mpcc_bot = NULL; in mpc3_init_mpcc()
1014 mpcc->blnd_cfg.overlap_only = false; in mpc3_init_mpcc()
1015 mpcc->blnd_cfg.global_alpha = 0xff; in mpc3_init_mpcc()
1016 mpcc->blnd_cfg.global_gain = 0xff; in mpc3_init_mpcc()
1017 mpcc->blnd_cfg.background_color_bpc = 4; in mpc3_init_mpcc()
1018 mpcc in mpc3_init_mpcc()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c1038 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc3_init_mpcc() argument
1040 mpcc->mpcc_id = mpcc_inst; in mpc3_init_mpcc()
1041 mpcc->dpp_id = 0xf; in mpc3_init_mpcc()
1042 mpcc->mpcc_bot = NULL; in mpc3_init_mpcc()
1043 mpcc->blnd_cfg.overlap_only = false; in mpc3_init_mpcc()
1044 mpcc->blnd_cfg.global_alpha = 0xff; in mpc3_init_mpcc()
1045 mpcc->blnd_cfg.global_gain = 0xff; in mpc3_init_mpcc()
1046 mpcc->blnd_cfg.background_color_bpc = 4; in mpc3_init_mpcc()
1047 mpcc in mpc3_init_mpcc()
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H A Ddcn30_mpc.h1089 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h296 uint32_t mpcc : 1; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h348 uint32_t mpcc : 1; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.c1389 phantom_pipe->update_flags.bits.mpcc = 1; in dcn32_apply_update_flags_for_phantom()

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